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Fully depleted GeOI (Germanium on Insulator) pMOSFETs with HfO2/TiN gate stack and Si-passivation are studied at low temperature. The impact of the starting Ge material and N-type channel doping on threshold voltage is examined. As there is no evidence of a background doping in Ge films, the typical parasitic conduction and threshold voltage shift in p-channel GeOI MOSFETs are due to interface states. An extended model predicting the threshold voltage temperature dependence in GeOI transistors is proposed.

The total dose irradiation effect on the SOI wafer is analyzed at the material level by pseudo-MOSFET technique. The proton irradiation induces positively charged traps in the buried oxide (BOX) and amphoterically charged traps at the film-BOX interface. The amphoteric interface trap charges contribute to the shift in threshold and flatband voltages by accentuating or attenuating the effect of the positive fixed charge in the BOX. The inherent ambipolar pseudo-MOSFET characteristics reveal both NMOS and PMOS properties, making it possible to identify and separate the charges that contribute to the shift of the turn-on voltage. The negatively charged acceptor-like states are located in the upper part of bandgap whereas the positively charged donor-like states are situated in the lower part of bandgap. These interface trap states can be removed by low-temperature annealing, so that only the oxide trapped charges continue to govern the turn-on voltage shift.

We have compared the short-channel effects (SCE) in triple-gate MOSFETs fabricated on SOI and strained SOI (sSOI) substrates. The triple-gate sSOI MOSFETs exhibit high gain in mobility but show earlier threshold voltage roll-off than unstrained devices. This indicates that the low effective mass and the narrow band-gap, due to tensile stress in sSOI substrate, increase the junction and gate tunneling leakage current and hence enhance the SCE. The off-current of sSOI device at Vg = 0 is one order of magnitude higher than that of SOI device, decreasing the on/off current ratio. The subthreshold slope of sSOI device is also affected. The stronger short-channel effect in sSOI device is correlated with a more intense channel-to-substrate coupling.

We present an overview of the single-transistor memory cells (1T-DRAMs), which are based on floating-body effects in SOI MOSFETs. The typical device architectures, principles of operation and key mechanisms for programming are described. The various approaches (Z-RAM, MSDRAM, etc) are compared in terms of performance and potential for aggressive scaling.

We have investigated the influence of subsequent annealing treatments in terms of gas ambient and duration on thickened GeOI substrates morphology and resistivity. A H2 bake seems to be more efficient than a N2 one to decrease the layer roughness and to increase the in-situ resistivity. The condensed GeOI (ρ GeOI) and the epi Ge layer (ρGe) resistivities have been extracted by considering the system as 2 parallel sheet resistances. After annealing treatment, ρGeOI is increased by a factor of 8 while the ρGe is increased by a factor of 2. The electrically active defects, acting like a p-type doping and created during both the Ge enrichment and the epitaxial thickening are cured by the annealing treatment. Thanks to this anneal, the blocking capability (i.e. full depletion) of pseudo MOSFET structures is strongly improved. The annealing parameters have a limited impact on the extracted values of the hole mobility.

In multiple-gate devices, coupling effects due to the 3-D architecture modify the electrical characteristics of the transistor. In this paper, electrical measurements have been carried out in order to examine the role of the back-gate voltage. In agreement with numerical simulations, it is shown that the back-gate influence is reduced for narrow devices due to a strong coupling between the different faces of the main gate. In narrow Fin devices, the Pi- and Omega-shapes of the gate provide an excellent electrostatic control of the field lines and potential, both in the buried oxide and in the silicon channel. The radiation-induced charge trapping in the BOX underneath the channel can be then much limited: narrow Fin devices exhibit a higher tolerance to ionizing radiations than its single-gate counterparts. Additionally, it is shown that the 2D dimensional coupling in these structures can be analytical calculated for Triple- and Pi-gate FETs. These models are compared with numerical simulations and show a very good agreement.

We discuss the origins of the transient gate current observed in the pseudo-MOS transistor in order to extract optional semiconductor parameters and its physical mechanisms. We analyze the time evolution of the gate current; its delay time is long even in quasi-static measurements at low gate voltages. Experiments show that the transient gate current characteristics are ruled by the generation-recombination process in the SOI layer and thermionic emission currents through the source and drain contacts. We address how the evaluate the generation-recombination lifetime in the SOI layer from the transient gate current behavior.

Based on electrical measurements and transmission electron microscopy imaging we propose in this paper a possible explanation for the measured mobility degradation with gate length reduction in short-channel MOSFETs. The carrier mobility in end-of-range implantation regions was investigated in Silicon-On-Insulator (SOI) and tensily-strained Silicon-On- Insulator (sSOI) substrates. Wafers with ultrathin films (from 8 to 35 nm) were Ge implanted at various concentrations, then annealed. The Pseudo-MOSFET measurements showed a mobility decrease (from 5 to 34%) as the implantation dose increased. The results are relevant for the optimization of the sources and drains regions of advanced nano-scale SOI transistors.

In this paper, we have investigated the influence of process parameters (bake temperature, bake duration and growth temperature) on the morphology of GeOI substrate thickened by Ge epitaxial regrowth. We have seen that the optimum bake temperature in terms of layer roughness and interfacial contamination is 600{degree sign}C. For higher bake temperatures, the layer morphology is 3D due to a layer dewetting. The efficiency of the surface preparation prior to the epitaxial regrowth has been assessed by Angle resolved X-Ray Photoelectrons Spectroscopy. No residual oxygen contamination has been detected. Furthermore, we have investigated the influence of the growth temperature on the layer morphology and resistivity. For temperatures higher than 450{degree sign}C, some thermal grooving assisted by the crystal defects (cross hatch) occurred and 3D Ge layers were obtained. Finally, GeOI substrates thickened with the best growth condition were evaluated by Pseudo MOSFET technique. An exceptional high hole mobility, beyond 400 cm2/V.s was observed.

We report a novel use of magneto-resistance (MR) to estimate carrier mobility in ultra-thin virgin SOI wafers. Measurements were made in pseudo-MOSFET configuration with electrical contacts in Corbino geometry and substrate biasing. The use of high magnetic fields enabled accurate extraction of electron mobility as a function of gate voltage (effective field) and film thickness. The MR mobility values are large and correlate well with the field-effect mobility determined in pseudo- MOSFETs at zero magnetic field.

We investigated the temperature dependence of the electrical properties of the MIGFETs, such as the drain current, the transconductance, the threshold voltage, the subthreshold slope and the field effect mobility. Devices with a gate length of 30 nm, a gate width of 30 nm and a silicon fin height of 100 nm were characterized at a temperature range between 77 K and room temperature. The MIGFETs were operated and compared in double- gate (DG) and single-gate (SG) modes in order to reveal the coupling effects between the various gates. The subthreshold slope in SG mode improves with decreasing temperature, but remains far from the ideal value measured in DG mode. The variations of the transconductance and mobility as a function of temperature are explained by strong coupling and series resistance effects. In DG mode, the mobility is highly improved due to volume inversion and reduced surface roughness scattering.