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aalso at E.E. Dept. KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium Since the 45 nm CMOS node, high-k gate dielectrics and strain engineering go hand in hand to further boost the transistor performance. An example of a so-called global strain platform relies on a thin strained-silicon (sSi) layer on top of a strain-relaxed Si1-xGex buffer (SRB) (Fig. 1). In addition, replacing thermally grown SiO2 by a deposited dielectric opens the door for the implementation of so-called high-mobility channel materials (Ge – pMOS; InxGa1-xAs – nMOS;...), which can be grown hetero-epitaxially on a silicon substrate. Due to the lattice mismatch of most of these materials with silicon, strain relaxation will occur above a certain critical thickness, leading to the introduction of both misfit and threading dislocations (TDs). It is well-known that dislocations introduce a one-dimensional band of states in the band-gap and hence are electrically active [1],[2]. The aim of the present review is to address the impact of such extended defects on the electrical performance of simple devices (p-n junctions, MOSFETs,...) for various high-mobility materials. A first example which will be discussed is the impact of TDs on the current-voltage (I-V) characteristics of p-n junctions fabricated in sSi and relaxed-Ge-on-Si substrates. As can be derived from Fig. 1, the depletion region mainly extends in the SiGe SRB, so that the electrical activity of the dislocations in this layer will be probed. It is clear from Fig. 2 that the reverse current IR of the diodes more or less proportionally increases with the density of TDs [3]. The same applies for the recombination and generation lifetime. Similar studies have been carried out for p-n junctions fabricated in a Si0.2Ge0.8 SRB and in relaxed Ge-on-Si epi layers. Summarizing all these results in Fig. 3, one can observe that the area leakage current density increases proportionally with the density of TDs and exponentially with the Ge content [4]. The latter can be explained by considering the impact on the band gap, yielding an exponential increase of the intrinsic carrier density. Comparing with Fig. 3b, it is clear that there exists a trade-off between leakage current density and epi layer thickness: thinner relaxed Ge layers on silicon will have a higher equilibrium TD density [5] and, hence, leakage current. However, considering a typical SRAM cell design, it can be concluded that for typical TDD values of 107-108 cm-2, the contribution to the off-state leakage is negligible compared with the contribution of the perimeter. A second example investigates the impact of anti-phase boundaries (APBs) on the reverse current of p-n junctions fabricated in GaAs (Fig. 4a) will be discussed. As can be derived from Fig. 4b, there is a modest increase of IRbetween on-axis junctions with a high APB density and off-axis diodes. Overall, it has been concluded that APBs are not so efficient leakage generators in GaAs. Finally, the impact of TDs on other device parameters, like the mobility or the threshold voltage of a MOSFET will be discussed. References [1] W. Schröter and H. Cerva, Solid State Phenomen., 85-86, p. 67 (2002). [2] E. Simoen et al., J. Electrochem. Soc., 158, p. R27 (2011). [3] G. Eneman et al., Appl. Phys. Lett., 87, p. 192112 (2005). [4] E. Simoen et al., J. Electrochem. Soc., 157, p. R1 (2010). [5] G. Wang et al., Appl. Phys. Lett., 94, p. 102115-1 (2009). Figure 1

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. Monolithic integration of III-V semiconductors epitaxially grown on Si substrate have been attracting much attention as building blocks for next-generation electronics and photonics due to their potential intrinsic properties. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active layers on Si. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy. We report here on the growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline V-groove structure in Si. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. As a conclusion, this study of III-V selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on (001) oriented Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is original and obviously confirm the potential of this heterogeneous integration option for high mobility logic devices, and photonic applications on a common Si platform.

The low-frequency noise is studied in planar InGaAs channel nMOSFETs, with Al2O3 gate dielectric in combination with different pre- and post-gate treatments, namely, pre-gate TMA exposure or post-gate Forming Gas Annealing (FGA). It is shown that the oxide trap density is reasonably uniform in the gate stack between 1 and 2 nm from the interface, whereby a FGA yields a lower noise power spectral density compared with the TMA or untreated devices.

Deep levels associated with extended and point defects in MOS capacitors fabricated on unintentionally doped GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep Level Transient Spectroscopy (DLTS). A 9nm layer of Al2O3 is deposited as high-k gate dielectric by Molecular Beam Epitaxy. The trap kinetics and origin of defect states is discussed. Also, it is shown that the dislocation cores in relaxed p-Ge are associated with band-like donor-like states in the lower half of forbidden band gap, and act as carrier trapping and recombination centers. In addition, slow and fast oxide interface traps are observed.

The effective passivation of germanium surfaces and interfaces has been claimed to be the key to a substantial progress in developing Ge-based microelectronic devices. This paper compares the currently most promising passivation routes, i.e. oxidation and sulfidation, focusing on the underlying atomic scale processes and highlighting similarities and discrepancies between both approaches. The effect of oxidation and sulfidation on electrically active defects is addressed, and the chemical and structural properties of the passivated surfaces are described in detail.

As post-Si era for digital device is incipient, In0.53Ga0.47As is good candidate among n-type active channels with high electron mobility but - unlike Si - it lacks a well-established technology for dielectric gating which may bear aggressive device scaling. Here we propose a viable route for the atomic layer deposition (ALD) of high-κ dielectrics taking advantage from the well-known self-cleaning effect of the trimethylaluminum (TMA) precursor on the III-V compound surfaces. In this respect, the incorporation of Al2O3 cycles both as pre-conditioning surface treatment and inside the ALD growth of a MO2 host matrix (M=Zr, Hf) is here investigated. Al:MO2/In0.53Ga0.47As heterojunctions have been scrutinized by in situ spectroscopic ellipsometry and ex situ chemical depth-profiling analysis which validate a good physical quality of the oxide and elucidate the effect of the pre-conditioning cycles at the interface level. The resulting MOS capacitors have been characterized by means of multifrequency capacitance-voltage measurements and conductance analysis therein yielding a permittivity of 19{plus minus}1 both for Al:HfO2 and Al:ZrO2 and similar electrical quality of the interfaces. On the other hand, Al:HfO2 appears to be electrically more robust against leakage and endowed with a lower frequency dispersion in accumulation.

We report two approaches to integrate high quality III-V templates with low defectivity on Si wafers by epitaxial growth. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagating from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

Deep levels present in MOS capacitors, fabricated on GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). The gate dielectric is composed of 9 nm Al2O3 deposited by Molecular Beam Epitaxy (MBE) on two different types of Interfacial Oxide Layers (IOL). It is shown that the density of interface traps (Dit) near the valence band edge is significantly reduced for GeSn epilayers compared with the same gate stack on a Ge cap. At the same time, several deep-level traps in the germanium depletion region have been observed, whereof the origin is discussed.

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 Ω.cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform.

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel for quantum well devices. In this work we first investigated building blocks such as passivation and contact resistances on both GaSb and InAs epilayer in order to define the optimal heterostructure for the quantum well device. In a second part, we focused on the growth studies of the complex heterostructure made with "6.1" semiconductors as well as the importance of the interface engineering with TEM. Finally, the properties of the optimized quantum well stack have been studied by means of photoluminescence and high resolution X-ray diffraction.

Three advanced architectures for ultimate progress in Ge p-Metal Oxide Semiconductor Field Effect Transistors are discussed in this paper. Different routes for stress implementations in Ge channels, either biaxial or uniaxial, are proposed by advanced selective Chemical Vapor Deposition techniques. Selective SiGe Strained Relaxed Buffer growth in Shallow Trench Isolation is first discussed to implement biaxial compressive strained Ge Quantum Wells on top of it. Next, innovative GeSn chemical vapor deposition technique is described in order to build either uniaxial strained Ge channel with GeSn Source/Drain stressors or compressively biaxial strained GeSn Quantum Well channels on Ge buffer layers.

CMOS scaling for sub-12 nm nodes will need high-mobility channel semiconductors such as III-V materials to be integrated on large diameter Si substrates. A way to overcome lattice mismatch is to confine defects resulting from strain relaxation on the sidewalls of trenches made by etch-back of Si in standard Shallow-Trench-Isolation (STI) structures. The surface of the InP layers, grown as buffer material in these trenches by selective epitaxy, is planarized by means of CMP, after which it needs to be recessed to allow for the deposition of the III-V channel stack. We have developed an in-situ HCl etching process allowing a close control of the recess depth down to a few nm and leaving a clean and planar InP surface well suited for subsequent III-V epitaxial growth. The process development was carried out in a commercial Aixtron Crius MOCVD reactor on standard SiO2 STI patterned 200 mm Si (001) wafers.

We will present the defect density at In0.53Ga0.47As and InP interfaces with ALD Al2O3 derived by use of the conductance method and from simulation of low frequency CV-curves. Consequences of the interface state distribution for MOS transistor device operation will be highlighted through 1-dimensional electrostatic simulations. The simulation results will be compared as much as possible to different state-of-the-art transistor results presented in literature.

The use of Ge and III/V materials for future CMOS applications is investigated. Passivation of the Ge surface can be obtained by either GeO2 or a thin Si layer. Short channel Ge pMOS devices with low EOT are fabricated. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are investigated and the performance of inversion channel MOSFET's on In0.53Ga0.47As with ALD Al2O3 is discussed.

Different selective epitaxial growth processes to deposit buried SiGe channels with Ge contents in the range of 25-55% and with an ultra thin Si capping layer have been successfully developed and implemented in pMOS device flows. Relatively low deposition temperatures assure the absence of SiGe islands and enable high quality strained SiGe layers. The required low growth temperature governed the choice of precursors used. In this contribution we review in detail the developed SiGe processes together with the deposition of the ultra thin Si cap layer. Electrical data obtained on the devices with incorporated Si0.75Ge0.25 and Si0.55Ge0.45 buried channels are presented as well.

We will shortly review the basic physics of charge carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high temperature CV-measurements are necessary for GaAs MOS characterization. The mid-gap trapping states in GaAs have characteristic emission times of the order of 1000 seconds, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures fasten these emission times, which makes measurements of the mid-gap traps possible with standard CV-measurements. CV-characterizations of GaAs/Al2O3, GaAs/Gd2O3, GaAs/HfO2 and In0.15Ga0.85As/Al2O3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to mid-gap energies, an electron trap peak close to mid-gap energies and an electron trap peak close to the conduction band.