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Ultra-thin HfO2 MOS capacitors on strained-Ge (s-Ge) have been fabricated with an extracted effective oxide thickness (EOT) of 4.9 A and leakage current less than 0.2 A/cm2. The CV measurements show no hysteresis and areal capacitance scaling for device sizes of 50x50 to 200x200 um2. A high series resistance is observed, likely due to a 500 meV valence band offset between the s-Ge and relaxed Si0.55Ge0.45 virtual substrate. The capacitance results suggest an extremely-scaled, high quality dielectric on s-Ge suitable for deeply scaled CMOS.

In this work, transport is explored in strained-Ge (s-Ge) p-MOSFETs with a hybrid GeOx/Al2O3/HfO2 gate stack directly on the channel with and without plasma post-oxidation (PPO). A gate-first process with ion implanted source/drains and a 625degC activation process was utilized. The gate stack is improved using PPO allowing for a demonstration of both extremely scaled CET (CET ~ 1.1 nm) and high mobility at high inversion charge. This demonstration suggests that this gate stack is a candidate for scaled s-Ge p-MOSFETs.

In this work, transport is explored in strained-Ge (s-Ge) p-MOSFETs with a hybrid GeOx/Al2O3/HfO2gate stack directly on the channel with and without plasma post-oxidation (PPO). A gate-first process with ion implanted source/drains and a 625°C activation process was utilized. The gate stack is improved using PPO allowing for a demonstration of both extremely scaled CET (CET ~ 1.1 nm) and high mobility at high inversion charge. This demonstration suggests that this gate stack is a candidate for scaled s-Ge p-MOSFETs.

Ultra-thin HfO2MOS capacitors on strained-Ge (s-Ge) have been fabricated with an extracted effective oxide thickness (EOT) of 4.9 Å and leakage current less than 0.2 A/cm2. The CV measurements show no hysteresis and areal capacitance scaling for device sizes of 50×50 to 200×200 µm2. A high series resistance is observed, likely due to a 500 meV valence band offset between the s-Ge and relaxed Si0.55Ge0.45virtual substrate. The capacitance results suggest an extremely-scaled, high quality dielectric on s-Ge suitable for deeply scaled CMOS.