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The feasibility of replacing the Au layer in a conventional ohmic contact of Ti/Al/Ni/Au for AlGaN/GaN structure with Cu has been investigated. While the thicknesses of Ti, Al and Cu layers were fixed throughout the study, the thickness of Ni layer was varied to examine its influence on the Cu-based ohmic contacts. It is showed that the Ni layer thickness played an important role in the Ti/Al/Ni/Cu metallization for achieving low contact resistance and smooth surface morphology. With a 50-A Ni layer, a low specific contact resistance (rc) of 1.35x10-6 ohm-cm2 has been realized. This result is comparable with the conventional ohmic contact (rc = 1.19x10-6 ohm-cm2). High electron mobility transistor (HEMT) devices fabricated using both Au- and Cu-based ohmic contact exhibited similar DC characteristics, suggesting that the electrical performance did not degrade with the used of Cu in the ohmic contact. Furthermore, in the absence of Au, the surface roughening caused by Au-Al alloy in the conventional ohmic contact was also prevented. As a result, the root-mean-square roughness of the optimized Cu-based contact was only 7.62 nm as compared to 134 nm for the conventional structure.

An effective passivation and gate insulator with low current collapse and improved dynamic ON-state resistance (RON) for GaN MIS-HEMT is demonstrated in this work. The structure of passivation and gate insulator is fabricated by 4-nm SiN as the first passivation layer and 1-nm AlN. The bilayer AlN/SiN structure integrates the advantages of SiN and AlN. SiN passivation has been proved to effectively reduce GaN surface states. AlN has high bandgap of ~6.2 eV which can suppress leakage current. Hence, the unfavorable effects such as trapping effect and leakage current which will induce current collapse and are effectively suppressed by using AlN/SiN bilayer thin film. A GaN MIS-HEMT with AlN/SiN passivation and gate dielectric exhibits improved I-V characteristics, low leakage current, low current collapse, and improved dynamic RON at high quiescent drain bias of 100 V.

Several characterizations of nanolaminate Al2O3/ZnO oxide films grown on Si substrates by using plasma enhanced atomic layer deposition (PE-ALD) method were studied. PE-ALD can minimize the structural imperfections in films and reduce substrate damage. The film deposition by using PE-ALD are dense, defect-free, highly uniform, conformal films and show excellent step coverage. Moreover, compared to other deposition techniques, it is possible to deposit high quality films at much lower temperatures. The High resolution transmission electron microscope (TEM) images showed the existence of sharp interfacial layers among the Al2O3, ZnO layer, and the Si substrate for the growth rate of 1.56 A/cycle, and the surface roughness of about 0.2 nm. The nanolaminate-stacking layer can be used in OLED encapsulation application as the gas barrier.

In this study, the growth of GaN-films-based light emitting diodes(LEDs), have been clearly demonstrated on wet-etching patterned sapphire substrate (PSS) and conventional LEDs. The wet-etching PSS LED device showed a significantly higher performance than the conventional LED device. The wet-etching PSS LED device exhibited a leakage current of 9 mA under a bias of 8 V, an external quantum efficiency and output powers of 35.09 % and19.23 mW under 20 mA injection current as compared to 12 mA, 27.23%, and 15.02 mW of the conventional LED device.

Ex-situ sulfide and HCl wet chemical treatments in conjunction with in-situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al2O3 on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. Capacitance-voltage (C-V) characterization of Al2O3/n-InAs structures shows that the frequency dispersion in accumulation regime is small (<0.75% per decade) and does not seem to be affected significantly by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the nMOS capacitors. The interface trap density profiles extracted from simulation show mainly donor-like interface states inside the InAs bandgap and in the lower part of the conduction band. The donor-like traps inside the InAs bandgap and in the lower part of the conduction band were significantly reduced by using wet chemical plus TMA treatments, in agreement with C-V characteristics.

The relationship between front contact pattern of GaAs single-junction solar cell with conversion efficiency at different concentration ratios is studied in this paper. Five different front circle-grid patterns were designed and patterned on the in-house fabricated single junction GaAs solar cells. At high light concentration ratio, the cell efficiency is strongly dependent on the series resistance of the electrode. At the same time, the thermal effect should also be taken into consideration, especially when a device is operating under high concentration ratio. Therefore, the aim of this work is to find a suitable front contact pattern for a GaAs single-junction solar cell to increase the conversion efficiency under high concentration solar radiation. It is found that the device with proper pattern design geometrical shadowing factor of 7.1% has the best cell efficiency of 27.05% at CR>100x, AM1.5G.

A discrete low noise In0.6Ga0.4As MHEMT with 150 nm gate length was flip-chip assembled on the low-cost RO3210 organic substrate for wireless communication applications. The measured DC characteristics were very similar before and after flip-chip assembly. The flip-chip packaged MHEMT showed a high drain current density of 516 mA/mm and a maximum transconductance of 576 mS/mm at a VDS of 0.8 V. The insertion gain of the flip-chip packaged device was decayed less than 2 dB up to 100 GHz as compared to the data of bare die. Moreover, the measured minimum noise figure was less than 2 dB as measured at VDS of 0.7 V and VGS of -0.7 V in the frequency range from 20 to 64 GHz for the device after flip-chip assembly. The excellent performance of the flip-chip packaged MHEMT demonstrates the feasibility of using low cost organic substrate for high frequency applications up to W band.

Post deposition annealing is a critical process for the quality improvement of gate oxides on - MOS capacitors. Though high temperature annealing would effectively repair defects, it could also induce undesired electrical characteristics due to the crystallization of the gate oxide. In this work, we investigate the novel two steps annealing technique to improve the HfO2/In0.7Ga0.3As MOSCAP properties. The two steps process takes advantage of 1st high temperature annealing (550deg) to improve the interface quality and 2nd low temperature annealing (450deg) for curing bulk oxide without oxide crystallization. The two steps annealing technique greatly improves the HfO2/In0.7Ga0.3As properties as compared to single step process and is expected to be helpful for future - MOSFET development.

An effective SiON passivation with high density of positive fixed charges for GaN MIS-HEMTs is demonstrated. The positive fixed charges at the SiON/AlGaN interface effectively reduce the surface potential and expand the quantum well below the Fermi level, thus improving the device performance. The GaN MIS-HEMT with SiON demonstrated a high maximum drain-source current density (IDS,max) of >1 A/mm, a breakdown voltage of 750 V at a drain leakage current of 1 uA/mm, and a well transfer characteristics. The dynamic ON-resistance only increased slightly under a high quiescent bias of 100 V.

The performance of n-type metal-oxide-semiconductor HEMTs with an InAs-channel using atomic-layer-deposited Al2O3 as gate dielectric has been fabricated and evaluated. The device performances of a set of scaled transistors with different gate dielectric thicknesses of 3, 5 and 7 nm have been investigated to determine whether the architecture of Al2O3 dielectric on InAs-channel HEMT can demonstrate good properties at low bias conditions for high-speed, high performance CMOS applications. The results indicate that the high-performance InAs-channel MOS-HEMTs with an ALD Al2O3 gate dielectric are promising candidates for advanced post-Si CMOS applications.

An eighty nanometer gate length InAs quantum well field effect transistors has been fabricated and the digital characteristics were evaluated. The devices show a drain-source current of 1015 mA/mm and a peak gm of 1920 mS/mm at VDS = 0.5 V. The fT and fmax are 340 GHz and 220 GHz at VDS = 0.4 V, respectively. A low delay time (CtotalV/ION) of 0.54 ps was also achieved. These excellent results indicate the InAs devices are the great potential option for the future low-power logic applications at post-Si CMOS technology.

The growth of the AlGaSb/InAs quantum well field effect transistor(QWFET) epitaxial structure on the Si substrate has been investigated. Buffer layers consisted of UHV/chemical vapor deposited grown Ge/GeSi and molecular beam epitaxy-grown AlGaSb/AlSb/GaAs were used to accommodate the strain induced by the large lattice mismatch between the AlGaSb/InAs QWFET structure and the Si substrate. A very high room-temperature electron mobility of 27300 cm2 /V s was achieved. Strained QWFET was also grown on the GaAs substrate, it is found that the strained QWFET grown on the Si substrate has higher electron mobility due to high strain induced in this structure.

An Indium Arsenic based quantum well field-effect transistors (QWFETs) with 80 nm gate length have been fabricated and evaluated for high speed and low DC power applications. The device exhibits high drain current density (1015 mA/mm), high transconductance (1920 mS/mm) and excellent RF performance (fT = 393 GHz), current gain cutoff frequency (fT), at an operating supply voltage of only 0.5 V. As for the gate delay time, the device shows a very low value of 0.54 psec at the VCC of 0.5 V. The InAs transistors demonstrate higher fT than silicon NMOS transistors while consuming smaller active power, indicating its great potential in next generation low power logic applications.

A low contact resistance Pd/Ge/Cu ohmic contact to n-type GaAs is successfully developed. The Pd/Ge/Cu ohmic contact exhibits a very low contact resistivity of 5.73 x 10-7 O-cm2 at a low annealing temperature (250 {degree sign}C). This result is comparable to the reported Pd/Ge and Au/Ge/Ni ohmic contact systems to n- type GaAs with doping concentrations about 1x1018 cm-3. The ohmic contact formation mechanisms and microstructure reactions were investigated using x-ray diffraction (XRD), secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM).

Plasma enhanced atomic layer deposition (PEALD) aluminum nitride (AlN) is attracting great interests as an advanced technique for high-k/III-V interfacial passivation. In this study, we demonstrate the effects of PEALD-AlN layer deposition plasma powers on the electrical properties of both n-type and p-type In0.53Ga0.47As based metal oxide semiconductor capacitors (MOSCAPs). By using PEALD-AlN as interfacial passivation layer (IPL) at the Al2O3/n, p-In0.53Ga0.47As interface, noticeable enhancement of electrical characteristics including small capacitance-voltage (C-V) hysteresis, small frequency dispersion values, and low interface state densities (Dit) have been observed. After performing 5 cycles of PEALD-AlN IPL at optimized plasma power of 150 W, multifrequency C-V responses exhibit excellent behaviors for both n-type and p-type Al2O3/AlN/In0.53Ga0.47As MOSCAPs. The Ditvalues are extracted to be 5.3 × 1011– 1.2 × 1012cm-2eV-1and 1.6 × 1011- 2.7 × 1011cm-2eV-1at the trap energy level of 0.47 – 0.4 eV and 0.2 – 0.26 eV above the edge of valence band (EV) for n-type and p-type MOSCAPs, respectively. X-ray photoelectron spectroscopy (XPS) analysis reveals that the enhancement of Dit values cannot be fully explained by the reduction of native oxides at the InGaAs surfaces. The original reason of interface defects states is attributed to the surface dangling bonds that were passivated by the polycrystalline PEALD-AlN passivation layer as illustrated in the high resolution transmission electron microscopy (HRTEM) image.

In this work, an effective N2plasma treatment for suppressing leakage current in GaN MIS-HEMT has been demonstrated. We observed an important issue of leakage current from the SiNx/GaN interface. To investigate the leakage current mechanisms, we measured the leakage current from all the possible paths in the device structure, such as gate, mesa isolation, and drain leakage. The current−voltage measurement results reveal a severe leakage path at the SiNx/GaN interface after SiNxdeposited on the GaN surface without N2plasma treatment. By using N2plasma treatment, we succeed in suppressing the leakage current and effectively improve breakdown voltage. A significant performance improvement of GaN MIS-HEMTs with very low leakage current has been achieved through the N2plasma treatment.

Ex-situ sulfide and HCl wet chemical treatments in conjunction with in-situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al2O3 on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. Capacitance-voltage (C-V) characterization of Al2O3/n-InAs structures shows that the frequency dispersion in accumulation regime is small (<0.75% per decade) and does not seem to be affected significantly by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the nMOS capacitors. The interface trap density profiles extracted from simulation show mainly donor-like interface states inside the InAs bandgap and in the lower part of the conduction band. The donor-like traps inside the InAs bandgap and in the lower part of the conduction band were significantly reduced by using wet chemical plus TMA treatments, in agreement with C-V characteristics.

The performance of n-type metal-oxide-semiconductor HEMTs with an InAs-channel using atomic-layer-deposited Al2O3 as gate dielectric has been fabricated and evaluated. The device performances of a set of scaled transistors with different gate dielectric thicknesses of 3, 5 and 7 nm have been investigated to determine whether the architecture of Al2O3 dielectric on InAs-channel HEMT can demonstrate good properties at low bias conditions for high-speed, high performance CMOS applications. The results indicate that the high-performance InAs-channel MOS-HEMTs with an ALD Al2O3 gate dielectric are promising candidates for advanced post-Si CMOS applications.

InGaAs MOS capacitors with HfO2 and La2O3 gate dielectrics have been investigated. La2O3 capacitor has revealed large leakage current. It can be considered that As atoms scattering into La2O3 layer from InGaAs substrate by annealing cause large leakage current. So, by inserting HfO2 in a substrate surface, La2O3/HfO2 stacking enables both the low leakage current as well as large capacitance density.