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In this study, the enhancement of the silicon etch rate with the heavy doping of phosphorus and arsenic was studied during cyclic selective epitaxial growth process using batch-type equipment. The reaction between molecular chlorine and heavily doped silicon was stimulated during the initial stage of cyclic SEG process at low temperature lower than 700° to induce voids at the interface. Heavy doping of n-type dopants into active regions also brought about the decrease in the growth rate of SEG process. It was possible to attain a stable process window by the elaborate control of total amount ratio of SiH4/Cl2. The window provided the robust interface between SEG silicon and active regions as well as the selectivity to an oxide layer. Vertical diodes which were realized within the window revealed eligible on- and off-current characteristics for cell switches applicable to next generation cross-point memories.

Abrupt changes in sidewall profile were induced in pulsed plasma etch process for high aspect ratio isolation trench structuring. Impacts of operational parameters when applying pulsed RF bias power were investigated. Silicon sidewall chipping problems were removed mainly by increasing bias power level and pulse frequency. The chemical sensitivity of O2 has shown decreased in extremely narrow trench spaces of high pattern density

We studied the misalignment between active and gate layer in terms of silicon dislocation caused by high temperature anneal process in SOG based STI gap-fill process. The SOG process is one of good candidates to overcome gap-fill limitation due to its excellent gap-fill characteristics. However, the SOG process needs high temperature anneal process to convert from Si-H, N-H to Si-O bond, which leads to the misalignment due to large stress change. We suggest that silicon defect is generated from ion bombardment at trench etch process and accelerated from hysteresis at anneal process. The O2 cure process is known as one of feasible methods to cure silicon damage through recrystallization. Based on this model, the misalignment was significantly improved as removing the defect through O2 cure process following trench etch process.

High-k dielectrics like Ta2O5, TiO2 etc. should overcome high leakage current due to the low energy band-gap property for applying to the future DRAM device below 50nm design rule beyond. Various techniques including metal doping and bi-layer scheme were studied to improve the leakage current of I-V characteristics. The leakage current of Dy or Zr doped TiO2 could be improved depending on the doping concentration. Nb doping in Ta2O5 could increase the dielectric constant within the appropriate level of leakage current at the operation voltage. Bi-layer scheme of high-k dielectrics like HfO2-TiO2 or ZrO2-TiO2 also applied to reduce the leakage current with the high work function Ru electrode. Combination of high work function Ru as a top electrode with the bottom TiN electrode could reduce the leakage current by increasing band offset at the interface between the high-k and the electrode.