1. Perpendicular Stt-Mram Scaling Challenges and Potential Solutions
- Author
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Tom Zhong, Luc Thomas, Guenole Jan, Jian Zhu, Huanlong Liu, Yuan-jen Lee, Son Le, Yu-Ring Tong, Dongna Shen, Renren He, Jesmin Haq, Jeffrey Teng, Santiago Serrano Guisan, Jodi Iwata-Harms, Sahil Patel, Vinh Lam, Yu-jen Wang, Terry Torng, and Pokang Wang
- Abstract
Significant progresses have been made in recent years in perpendicular spin torque transfer magnetic random access memory (pSTT-MRAM) technology development by many companies or organizations. Commercialization of pSTT-MRAM is more real today than ever in the long history of MRAM technology development. We have recently reported fully functional pSTT-MRAM chips and macros with sub-5ns writing speed based on 90nm and 40nm node CMOS technologies [1,2]. These technologies can be potentially used to replace current embedded non-volatile memories such as embedded flash memories or SRAM and be applies to energy efficient applications such as internet of thing (IOT). In this presentation, we will review recent progresses and discuss STT-MRAM scaling challenges for product at 28nm technology node and beyond in terms of integration schemes as well as magnetic and electrical transport properties. We will also discuss the potential solutions that we see for these challenges. References: [1] G. Jan, Symp VLSI Tech, 2014. pp 50-51. [2] Yu Lu et al, IDEM Technical Digest, 2015 (in press)
- Published
- 2016
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