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A Nanostructured GaN Device Architecture for Power Applications Z. John Shen, Gourab Sabui, Vitaly Z. Zubialevich, Mary White, Pietro Pampili, Peter J. Parbrook, Mathew McLaren, Miryam Arredondo-Arechavala Gallium nitride (GaN) has emerged as a promising material for development of power semiconductor devices owing to its high critical electric field, large bandgap and superior transport properties. The unique properties of GaN have prompted realization of power devices both in a lateral (high electron mobility transistors (HEMTs)) and a vertical layout (bulk GaN on GaN devices). GaN power devices show extremely low conduction and switching losses and holds the key to extremely low-loss and high-efficiency power converters of the future. However, GaN power devices have been plagued with several inherent drawbacks preventing a ubiquitous adoption of GaN as the material of choice for power switches. The most critical trade-off has been the choice of substrate for the growth of GaN epitaxy: a high performance, high-cost native substrate against a low-cost, non-native substrate with associated reliability issues. For GaN to thrive as a superior successor to Si, a low cost, high performance epitaxy with improved reliability is expected moving forward. Current lateral HEMTs and vertical GaN on GaN devices are inadequate to address this trade-off. A novel nanostructured approach to GaN power devices is proposed in this paper. The unique property of GaN nanowires is its ability to elastically relax in the lateral direction, and accommodate lattice mismatch with non-native substrate through pseudomorphic growth without dislocation formation as compared to thin-film heterostructures. Experimental studies have shown self-induced GaN NWs grown with a high surface to volume ratio on a Si substrate have a non-polar side face and is virtually free of threading dislocations and other structural defects. Power devices grown on a nano-GaN epitaxy theoretically have the potential to bypass the reliability concerns associated with a non-native substrate but still deliver comparable or even superior performance, albeit at a low-cost. Schottky barrier diodes are designed and fabricated based on the nano-GaN concept. Fabricated diodes grown on a Sapphire substrate show distinct rectifying properties blocking voltages of 100 V. Despite repetitive biasing, the devices did not show any sign of current collapse. Design optimization of the nanowire Schottky barrier diode (NWSBD) is performed using 3D TCAD drift-diffusion simulations and semiconductor-oxide interaction was utilized to push the performance of the NWSBDs beyond the unipolar limit of GaN. The optimized NWSBD show the potential to block voltages upwards of 650 V working under present fabrication constraints of doping concentrations and pillar height. Simulated characteristics predict superior VRB 2/RON FoM, outperforming both the lateral HEMTs and the vertical GaN on GaN devices. A fully controlled, three terminal nanowire field effect transistor (NWFET) is also investigated using 3D TCAD drift-diffusion modeling. The NWFET can be operated in both normally-off and normally-on modes based on design and requirements. The 3D gate around the nanowires coupled with a strong dielectric REduced SURface Field (RESURF) effect allows this architecture to block voltages beyond the 1D unipolar material limit of GaN in the reverse bias. With proper design, highly desirable linear voltage to pillar height scaling can be achieved for the NWFET. Breakdown voltages of more than 900 V is predicted, with superior VRB 2/RON and QGD x RDS(ON) figure of merits. Despite lacking a body-diode, the NWFETs being quasi-symmetrical enables current conduction in the 3rd quadrant itself by self-commutated reverse conduction with a very low voltage drop. The nanowire architecture holds great potential to produce power rectifiers and controlled FETs with high performance, improved reliability and ruggedness and in a cost-effective way.