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Start Over Author "Horiguchi, N." Journal ecs journal of solid state science and technology
7 results on '"Horiguchi, N."'

3. Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations

Author

Dabral, A., primary, Pourtois, G., additional, Sankaran, K., additional, Magnus, W., additional, Yu, H., additional, de Jamblinne de Meux, A., additional, Lu, A. K. A., additional, Clima, S., additional, Stokbro, K., additional, Schaekers, M., additional, Collaert, N., additional, Horiguchi, N., additional, and Houssa, M., additional

Published
2018
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4. Processing Technologies for Advanced Ge Devices

Author

Loo, R., primary, Hikavyy, A. Y., additional, Witters, L., additional, Schulze, A., additional, Arimura, H., additional, Cott, D., additional, Mitard, J., additional, Porret, C., additional, Mertens, H., additional, Ryan, P., additional, Wall, J., additional, Matney, K., additional, Wormington, M., additional, Favia, P., additional, Richard, O., additional, Bender, H., additional, Thean, A., additional, Horiguchi, N., additional, Mocuta, D., additional, and Collaert, N., additional

Published
2016
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7. Processing Technologies for Advanced Ge Devices

Author

Loo, R., Hikavyy, A. Y., Witters, L., Schulze, A., Arimura, H., Cott, D., Mitard, J., Porret, C., Mertens, H., Ryan, P., Wall, J., Matney, K., Wormington, M., Favia, P., Richard, O., Bender, H., Thean, A., Horiguchi, N., Mocuta, D., and Collaert, N.

Abstract

With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

Published
2017
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