28 results on '"Gerd Ascheid"'
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2. Self-Supervised Quantization of Pre-Trained Neural Networks for Multiplierless Acceleration.
3. An Efficient Bit-Flip Resilience Optimization Method for Deep Neural Networks.
4. OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation.
5. Accurate neuron resilience prediction for a flexible reliability management in neural network accelerators.
6. Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack.
7. SystemC-link: Parallel SystemC simulation using time-decoupled segments.
8. Optimized buffer allocation in multicore platforms.
9. A flexible ASIP architecture for connected components labeling in embedded vision applications.
10. Time-decoupled parallel SystemC simulation.
11. Automatic detection of concurrency bugs through event ordering constraints.
12. High-level modeling and synthesis for embedded FPGAs.
13. Hybrid simulation for extensible processor cores.
14. Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms.
15. High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.
16. Retargetable Code Optimization for Predicated Execution.
17. Design space exploration of partially re-configurable embedded processors.
18. Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.
19. Automatic ADL-based operand isolation for embedded processors.
20. An interprocedural code optimization technique for network processors using hardware multi-threading support.
21. A SW performance estimation framework for early system-level-design using fine-grained instrumentation.
22. C Compiler Retargeting Based on Instruction Semantics Models.
23. A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.
24. A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.
25. A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.
26. RTL Processor Synthesis for Architecture Exploration and Implementation.
27. Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing.
28. System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures.
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