52 results on '"GEORGES G"'
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2. End-to-End Optimization of High-Density e-Skin Design: From Spiking Taxel Readout to Texture Classification.
3. EffiCSense: an Architectural Pathfinding Framework for Energy-Constrained Sensor Applications.
4. Circuit models for the co-simulation of superconducting quantum computing systems.
5. Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs.
6. Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories.
7. Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS.
8. A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks.
9. Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping.
10. Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection.
11. A fast analog circuit yield estimation method for medium and high dimensional problems.
12. Advances in variation-aware modeling, verification, and testing of analog ICs.
13. Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors.
14. Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation.
15. Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model.
16. Stochastic circuit reliability analysis.
17. Systematic design of a programmable low-noise CMOS neural interface for cell activity recording.
18. Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity.
19. An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique.
20. Health-care electronics The market, the challenges, the progress.
21. Efficient reliability simulation of analog ICs including variability and time-varying stress.
22. Massively multi-topology sizing of analog integrated circuits.
23. A design methodology for fully reconfigurable Delta-Sigma data converters.
24. Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies.
25. An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection.
26. Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns.
27. Top-down heterogeneous synthesis of analog and mixed-signal systems.
28. CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming.
29. Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces.
30. Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series.
31. Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
32. Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.
33. Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines.
34. A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design.
35. Digital Ground Bounce Reduction by Phase Modulation of the Clock.
36. HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits.
37. A Model of Computation for Continuous-Time ?-? Modulators.
38. Generalized Posynomial Performance Modeling.
39. Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver.
40. Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors.
41. Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter.
42. Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices.
43. A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics.
44. High-level simulation of substrate noise generation from large digital circuits with multiple supplies.
45. Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model.
46. A Power Estimation Model for High-Speed CMOS A/D Converters.
47. Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon.
48. From Transistor to PLL - Analogue Design and EDA Methods.
49. Figure of Merit Based Selection of A/D Converters.
50. Design challenges and emerging EDA solutions in mixed-signal IC design.
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