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Achieving low conduction loss and good channel mobility is crucial for SiC MOSFETs. However, basic planar SiC MOSFETs provide challenges due to their high density of interface traps and significant gate-to-drain capacitance. In order to enhance the reverse recovery property of the device, a Schottky barrier diode (SBD) was added to the source contact area, the top of the current spreading region, of a trench-etched double-diffused SiC MOS (TED MOS). Two types of SBD structures were optimized to improve the electrical properties using 3D simulation software, “TCAD Silvaco”. During reverse recovery simulation, the carriers of the device were withdrawn from the SBD, indicating that the new design was effective. It also showed that the recovery properties of the new design depended on temperature, carrier lifetime, and the work functions of metals. All the new designs were evaluated in various circumstances to determine the trend. Ultimately, in high-speed switching circuits, the SiC TED MOS with SBD structure efficiently boosted switching speed, while reducing switching loss.

In this paper, DC, transient, and RF performances among AlGaN/GaN HEMTs with a no field plate structure (basic), a conventional gate field plate structure (GFP), and a double floating field plate structure (2FFP) were studied by utilizing SILVACO ATLAS 2D device technology computer-aided design (TCAD). The peak electric fields under the gate in drain-side can be alleviated effectively in 2FFP devices, compared with basic and GFP devices, which promotes the breakdown voltage (BV) and suppresses the current collapse phenomenon. As a result, the ON-resistance increase caused by the current collapse phenomena is dramatically suppressed in 2FFP ~19.9% compared with GFP ~49.8% when a 1 ms duration pre-stress was applied with Vds = 300 V in the OFF-state. Because of the discontinuous FP structure, more electric field peaks appear at the edge of the FFP stacks, which leads to a higher BV of ~454.4 V compared to the GFP ~394.3 V and the basic devices ~57.6 V. Moreover, the 2FFP structure performs lower a parasitic capacitance of Cgs = 1.03 pF and Cgd = 0.13 pF than those of the GFP structure (i.e., Cgs = 1.89 pF and Cgd = 0.18 pF). Lower parasitic capacitances lead to a much higher cut-off frequency (ft) of 46 GHz and a maximum oscillation frequency (fmax) of 130 GHz than those of the GFP structure (i.e., ft = 27 GHz and fmax = 93 GHz). These results illustrate the superiority of the 2FFP structure for RF GaN HEMT and open up enormous opportunities for integrated RF GaN devices.

In the traditional SJ MOSFET structure, n/p pillars with the same doping concentrations in the drift region are introduced to decrease the on-resistance. However, SJ MOSFET will turn on the parasitic diodes due to fast reverse recovery, further inducing severe oscillation in the reverse recovery of the device and the corresponding adverse effect on the circuit. In this study, a fast recovery vertical superjunction (SJ) MOSFET with n-Si and p-3C-SiC pillars was studied. Unlike other structures, such as the 4H-SiC superjunction UMOSFET with a heterojunction diode or the ultra-low recovery charge cell-distributed Schottky contacts SJ-MOSFET with integrated isolated NMOS, we introduce a Schottky barrier diode (SBD) on the source contact at the top of the n-Si pillar in the SJ-MOSFET to improve the device reverse recovery. The simulation software TCAD Silvaco was utilized to simulate the device properties. Compared with the conventional Si SJ, the proposed Si/SiC SJ with the Schottky barrier diode (SBD) connected demonstrated a lower reverse recovery charge, which was reduced by 90.5%, respectively. The waveform of the reverse recovery current demonstrates that the electrons in the device are withdrawn from SBD during reverse recovery, preventing the opening of the parasitic diode in the SJ MOSFET. Finally, another structure is illustrated to decrease the gate capacitance by introducing a thin p-base layer between the gate metal and N-Si pillar so that it can improve the switching characteristics of devices. The open-loss and off-loss of the improved device were reduced by 33% and 42.3%, respectively.

This paper studied an atomic layer etching (ALE) technique with a surface treatment function for InAlN/GaN heterostructures with AlN spacer layers. Various parameters were attempted, and 30 s O2 + 15 W BCl3 was chosen as the optimal recipe. The optimal ALE approach exhibited satisfactory etching results, with regard to the etch-stop effect, compared with other techniques. The atomic force microscopy (AFM) results showed an etching per cycle (EPC) value of 0.15 nm/cycle, with a 0.996 fit coefficient and root mean square (RMS) surface roughness of around 0.61 nm (0.71 nm for as-grown sample), which was the lowest in comparison with digital etching (0.69 nm), Cl2/BCl3 continuous etching (0.91 nm) and BCl3 continuous etching (0.89 nm). X-ray photoelectron spectroscopy (XPS) and scanning transmission electron microscopy with energy dispersive X-ray spectroscopy measurements (STEM/EDS) verified the indium clustered phenomena at the bottom apex of V-pit defects in the epi structure of InAlN/GaN high electron mobility transistors (HEMTs) for the first time, in addition to the surface morphology optimization for the ALE under-etching technique used in this work. The resistor hall effect (Hall) and AFM measurements demonstrated that after 4 or 5 ALE cycles, the two-dimensional electron gas (2-DEG) density and RMS roughness were improved by 15% and 11.4%, respectively, while the sheet resistance (Rsh) was reduced by 6.7%, suggesting a good surface treatment function. These findings were important for realizing high-performance InAlN/GaN HEMTs.

The contact resistance between graphene and metal electrodes is crucial for the achievement of high-performance graphene devices. In this study, we review our recent study on the graphene–metal contact characteristics from the following viewpoints: (1) metal preparation method; (2) asymmetric conductance; (3) annealing effect; (4) interfaces impact.