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Focuses on the efforts of the Institute of Electrical and Electronics Engineers (IEEE) and the Open Verilog International (OVI) committee to develop analog extensions to VHDL and Verilog. Verilog-A's use of a probe/source model; Difficulty involved in simulating complex circuits in the early stages of the design process; Features of available analog simulators. INSET: Postscript..

Reports on industry standards-setting organization Open Verilog International's (OVI) approval of the analog and mixed-signal (AMS) standard called Verilog AMS for the Verilog hardware description language (HDL). Basis of the Verilog AMS; Support of the industry for the Verilog AMS.

Reports on developments related to hardware-description languages (HDL). Market data from Electronic Design Automation Cos.; Proponents of the VHDL and Verilog languages.

Reports on Cadence Design Systems' announcement of the transfer of ownership of the Verilog-A specification to Open Verilog International (OVI). OVI's plans for the specification; Background on the Verilog-A specification.

Features products and joint-development projects related to Verilog hardware description language. Includes the integration of FrontLine Design Automation's BaseLine Verilog simulator into Data I/O's Synario software; Chronologic Simulation's Verilog Compiled Simulator 3.0; Ikos' Voyager Series.

Focuses on the benefits of combining C computer program languages to Verilog hardware description languages (HDL) at Ericsson. Features of the design operations at Ericsson; Benefits of the addition of a C code to a Verilog simulator; Other applications of Verilog in the company's operations.

Reports on the unveiling of the Language Reference Manual (LRM) for the Verilog computer hardware description language at the annual meeting of Open Verilog International in March 1996. Functions and features of LRM; Purpose of Open Verilog's Verilog-A LRM.

Reports on the effects of the `Portable Library Rationalization' efforts of Meta-Software's Kima Hailey on the creation of analog extensions to VHDL and Verilog computer hardware description languages.

Reports on the availability of an OVI-compliant RC-simulator option to interHDL's Viper Verilog HDL simulator. RCsim as the name of the RC-simulator; Tight coupling of the simulator to Viper; Accuracy of RCsim.