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Various technological developments in the microprocessor world make modern computing systems more vulnerable to soft errors than in the past, and consequently fault tolerance techniques are becoming increasingly important in various application domains. While in general fault tolerance methods are known to achieve high levels of reliability, they can also introduce significant performance, energy, and memory overheads, which can be reduced by employing such techniques selectively, as opposed to indiscriminately. Data Replication is used to prevent error propagation across hardware components and application program data structures by replicating application program's data. When using data replication, many factors need to be taken into account, including which data structures/elements to replicate, how many times to replicate a given data element, and which threads to protect (in a multithreaded application). These and similar factors define what can be termed as "replication space". This study defines a replication space, and systematically explores protection techniques of various strengths/degrees, quantifying their impacts on memory consumption, performance, and error propagation. Our experimental analysis reveals that different degrees of protection levels bring different outcomes based on the application specifics. In particular, while error propagation is limited, to a certain extent, when employing data replication in multithreaded applications where the thread do not communicate/share data much, the speed of error propagation across threads can be quite fast in applications where threads are more tightly coupled. Additionally, our results indicate that in certain cases where error propagation is low, the effect of data replication on error propagation can be negligible. [ABSTRACT FROM AUTHOR]

Cache structures in a multicore system are more vulnerable to soft errors due to high transistor density. Protecting all caches unselectively has notable overhead on performance and energy consumption. In this study, we propose asymmetrically reliable caches to supply reliability need of the system using sufficient additional hardware under the performance and energy constraints. In our framework, a chip multiprocessor is composed of a high reliability core which has ECC protection, and a set of low reliability cores which have no protection on their data caches. Between two types of cores, there is also a middle-level reliability core which has only parity check. Application threads are mapped on the different cores in terms of reliability based on their critical data usage. The experimental results for selected applications show that our proposed techniques improve reliability with considerable performance and energy overhead on the average compared to traditional unsafe caches. [ABSTRACT FROM AUTHOR]

This paper presents two parallel formulations for the Barnes-Hut algorithm on the Cell architecture, which differ in tree distribution and construction phases of the algorithm. In the initial parallelization, the domains are dynamically partitioned and assigned to the synergistic processing elements (SPEs), and SPEs construct local trees of the sub-domains in parallel. The enhanced parallelization scheme provides better clustering of the particles by sequentially constructing the global tree of the entire work space in the power processing element (PPE) and by partitioning the tree into sub-trees that can fit in the Local Store. SPEs operate on the sub-tree data and construct local trees in parallel. Our experimental evaluation indicates that this application performs much faster on the Cell BE compared to the Intel Xeon based system. Specifically, our first and second methods on the Cell BE outperform Intel Xeon by a factor of 5.8 and 7.1 for 8192 particles, respectively. [ABSTRACT FROM AUTHOR]