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The channel mismatches, particularly the gain and the timing skew errors degrade significantly the performance of high-speed Time-Interleaved Analog-to-Digital converters (TIADCs). The error correction using blind calibration methods is difficult because of the correlation between the input signal and the noise signal caused by these channel mismatch errors. In this paper, a new fast convergent algorithm is proposed to correct the gain mismatch and timing skew errors. This new algorithm is based on oversampling and guarantees the independence of the signal and the noise. To estimate noise produced by gain mismatch and timing skew error, a new structure based on modulation concept is developed. The proposed adaptive compensation structure has fast convergence speed using an accurate estimated error signal and a simple cost function. The proposed structure unlike other oversampling-based algorithms is applicable in narrow-band signals by selecting the optimum oversampling ratio. The proposed algorithm is simulated using a four-channel TIADC with 10-bit resolution. Theoretical analysis and simulation results verified the fast convergence speed and the good performance of the proposed algorithm for both narrow-band and wide-band signals. [ABSTRACT FROM AUTHOR]

Over the last few years, deep learning on irregular 3D data given its wide range of applications has become one of the active topics in the field. While field programmable gate array (FPGA)-based acceleration of deep learning models has been proved to produce power-efficient designs in comparison with other platforms such as CPUs and GPUs, only a few studies have been conducted regarding the models that consume point clouds as their input. Although tailoring the hardware designs to specific networks could lead to better optimization opportunities, it is also important to keep the reusability of the design in mind, especially for a new and evolving topic like learning on point clouds. In this work, we have aimed to achieve reusability by keeping the hardware isolated from the computational graph. Considering the numerous types of layers used in dynamic graph convolutional neural network (DGCNN) and its popularity, our proposed design aims for the thorough acceleration of DGCNN. The challenges including 18 types of tensor operations, achieving burst transfers, dealing with kernel complexities, external memory banks, in-order and out-of-order execution modes, and approaches with multiple processing elements have been explained in details throughout the paper. Our experiments on a single FPGA with a single bitstream, DDR4 memory subsystem, and Float32 data type demonstrated speedups of 2.73 × to 8.4 × compared to a sequential single-threaded implantation on an Intel Core i7 6700HQ. [ABSTRACT FROM AUTHOR]