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This paper presents a delay-locked loop (DLL) with multiple radiation-hardened techniques. A radiation-hardened charge pump (RH-CP) and a radiation-hardened voltage-controlled delay line (RH-VCDL) are proposed to mitigate effects on DLLs caused by single-event transient (SET). A lock detection module (LDM) is designed in the RH-CP to separate CP and VCDL when the DLL is locked. Thanks to LDM, the voltage transients caused by ion strikes on CP can be prevented from effecting the control voltage of VCDL and causing inverted lock error. A SET correction module (SCM) combined with sliced delay cells is used in the RH-VCDL to select the uncorrupted output and avoid missing pulses errors occurring at the output of DLL. The proposed DLL is designed in 22-nm CMOS process with an operation frequency of 5 GHz. Simulations at linear energy transfer (LET) between 40 and 100 MeV-cm2/mg show that RH-CP eliminates inverted lock error and RH-VCDL mitigates missing pulses generated by the DLL after ion strikes effectively. [ABSTRACT FROM AUTHOR]

In this paper, a programmable low-power analog front-end (AFE) integrated circuit (IC) for biomedical signal monitoring systems is presented. The whole system includes four parts, instrumentation amplifiers (IA), programmable gain amplifiers (PGA), programmable bandwidth filters (PBF) and successive approximation register analog-to-digital convertors (SAR ADC). The proposed IA employs a pseudo-differential structure to enhance the input impedance of the system. A novel hybrid bandwidth extension technology is introduced in the proposed PGA to correct the low-frequency distortion and improve the low-frequency bandwidth. In the design of PBF, the current steering technology is applied to achieve an area-efficient and energy-efficient architecture. Furthermore, a novel efficient switching scheme and a self-calibration dynamic element matching method are presented in the design of SAR ADC to reduce the power consumption and eliminate the effect of capacitor mismatch. In 0.18 μm CMOS technology, this AFE IC consumes 46.8 μW and occupies 0.36 mm2. It achieves a variable gain from 40.4 to 55.1 dB under different modes designed for different biomedical signals. The spurious-free dynamic range and signal-to-noise plus distortion ratio of the proposed SAR ADC are 71.3 and 53.3 dB, respectively, along with a figure of merit of 0.18 pJ/conv. [ABSTRACT FROM AUTHOR]

This paper presents a low-power asynchronous 8-bit 500MS/s 2b/cycle successive-approximation-register (SAR) analog-to-digital converter (ADC) in 40 nm CMOS process. The proposed ADC shows high energy efficiency and good performance against process–voltage–temperature (PVT) variations by a background offset mismatch calibration technique, a supply voltage calibration technique and an efficient 2b/cycle switching scheme. The background offset mismatch calibration eliminates the effect of offset mismatches of the comparator array without any extra phase. The supply voltage calibration is presented to monitor the conversion speed of the ADC and adjust the speed of comparators to ensure the ADC can work properly at different process corners. The improved switching scheme helps cut down the switch times and simplifies the switch logic, which saves 87.8% switching energy compared with conventional VCM-based scheme. The proposed SAR ADC simulated a signal-to-noise plus distortion ratio (SNDR) of 45.8 dB and a spurious-free dynamic range (SFDR) of 55.5 dB for a near-Nyquist input while consuming a total power of 2.59 mW, culminating in a Walden figure of merit (FoM) of 32 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

An ultra-low power consumption two-stage mixed switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented. Using two simple switches, the novel switching scheme divides the capacitor arrays into two sub-arrays: stage-one and stage-two arrays. The two sub-arrays convert high and low bits cycles, respectively. Once the high bits conversion cycles are completed, the corresponding sub-arrays are split off from the capacitor arrays. This decreases the number of capacitors used in the rest conversion procedure. Thus, the proposed method improves the energy efficiency of SAR ADC. Thanks to C–2C dummy capacitors and two-stage capacitor arrays, the novel architecture achieves 86% reduction in capacitor area than conventional SAR ADC. Furthermore, based on the charge sharing technique and monotonic switching method, the proposed switching scheme does not consume reset energy and achieves 99.8% less switching energy than the conventional switching method. In addition, the proposed scheme is less sensitive to capacitor mismatch because of its great performance in linearity. [ABSTRACT FROM AUTHOR]