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Sn-doped Ge2Sb2Te5 thin films deposited on Si(100)/SiO2 substrates by rf magnetron sputtering are investigated by a differential scanning calorimeter, x-ray diffraction and sheet resistance measurement. The crystallization temperatures of the 3.58 at.%, 6.92 at.% and 10.04 at.% Sn-doped Ge2Sb2Te5 thin films have decreases of 5.3, 6.1 and 0.9°C, respectively, which is beneficial to reduce the switching current for the amorphous-to-crystalline phase transition. Due to Sn-doping, the sheet resistance of crystalline Ge2Sb2Te5 thin films increases about 2–10 times, which may be useful to reduce the switching current for the amorphous-to-crystalline phase change. In addition, an obvious decreasing dispersibility for the sheet resistance of Sn-doped Ge2Sb2Te5 thin films in the crystalline state has been observed, which can play an important role in minimizing resistance difference for the phase-change memory cell element arrays.

Ag-doped Ge2Sb2Te5 films were deposited by rf magnetron sputtering on SiO2/Si substrates. The content of Ag ranging from 4.5 to 11.3 at.% is determined by inductively coupled plasma atomic emission spectrometry. The crystallization temperature of Ag-doped Ge2Sb2Te5 increases with the increasing Ag content and the stability of phase change film is improved greatly. Structures were measured by x-ray diffraction and the face-centered-cubic structure was more stable after Ag doping. Four-point probe was used to measure the sheet resistance of Ag-doped Ge2Sb2Te5 films annealed at different temperatures and it is indicated that Ag atoms increase the sheet resistance of Ge2Sb2Te5 thin film when the annealing temperature is higher than about 360 degrees C, which is beneficial for reducing the reset current. Current-voltage curves were tested and it is demonstrated that 4.5 at.% Ag doping into the Ge2Sb2Te5 film can reduce the threshold current from 1.46 mA to 0.25 mA and can only increase the threshold voltage slightly, which is very useful for low energy consumption.

A single nano-cell-element of chalcogenide-random access memory was fabricated by using the focused ion beam method. The minimum contact size between the Ge2Sb2Te5 phase change film and the top electrode film for the cell element is with diameter of 60 nm. The reversible phase transition between the RESET state and the SET state was successively realized. The minimum SET current is obtained to be about 0.28 mA.

The effect of annealing temperature on crystallization of amorphous Ge2Sb2Te5 films with thickness of 40 nm is studied by TEM and AFM methods. The relationship between microstructure and resistivity of the Ge2Sb2Te5 film is investigated. From the TEM measurements, the grain size of crystallites increases gradually as the annealing temperature increases. When the annealing temperature is too high, voids are formed, which may originate from evaporation of the Ge2Sb2Te5 film at the elevated temperatures, formation of sink, being nucleated by residual vacancies, and surface roughness. The resistivity of the Ge2Sb2Te5 film decreases with the increasing annealing temperature and has slight changes when the temperature is higher than 400 degrees C. Phase transitions and scattering of crystallite boundaries may be the major factors affecting the resistivity of the Ge2Sb2Te5 film.

Amorphous zirconia thin films were deposited directly on silicon-on-insulator (SOI) substrates with thin top silicon by ultra-high vacuum electron beam evaporation. Spreading resistance profile and scanning transmission-electron microscopy (TEM) were used to detect the interface quality and microstructure, revealing that the interface between the zirconium oxide films and top silicon was abrupt and clear. The films kept to be amorphous up to the rapid thermal temperature of 700°C for 300 s, but arriving at 700°C an unknown interfacial product appeared, which was probably ZrSixOy. High frequency capacitance-voltage (C-V) characteristics at 1 MHz performed on metal-oxide-SOI structure revealed that this interfacial product exhibited good electrical properties of zirconia thin films. When the annealing temperature increased from 600°C to 700°C, flat voltage VFB changed from -2.451 to -1.741 eV, showing the improvement in the quality of the films. The cumulative region capacitance decreased from 3.058×10-11F to 3.012×10-11F, indicating increasing equivalent oxide thickness, which is in agreement with the result of high-resolution cross-sectional TEM.

Si16Sb84-based line cell phase change random access memory (PCRAM), in which the Si16Sb84 phase change line is contacted by TiN electrodes with a nanoscale gap, is fabricated by electron beam lithography The lowest current and measured pulse width for RESET operation are 115 μA and 18 ns, respectively The measured shortest pulse width for recrystallization is 110ns, with applied pulse amplitude of 1.5 V. SET and RESET currents for line cells with different line lengths are determined. Endurance of 106 cycles with a resistance ratio of above 800 has been achieved.

In order to improve the reliability of C-RAM devices, a seamless sub-micro W heating electrode in diameter 260 nm is fabricated with standard 0.18 μm CMOS processing line. Then we successfully manufacture a chalcogenide random access memory device using this seamless sub-micro W heating electrode. The results show good electrical performance, e.g. the reset current of 1.3 mA and the set/reset cycle up to 109 have been achieved.

In order to improve nano-scale phase change memory performance, a super-clean interface should be obtained after chemical mechanical polishing (CMP) of Ge2Sb2Te5 phase change films. We use reactive ion etching (RIE) as the cleaning method. The cleaning effect is analysed by scanning electron microscopy and an energy dispersive spectrometer. The results show that particle residue on the surface has been removed. Meanwhile, Ge2Sb2Te5 material stoichiometric content ratios are unchanged. After the top electrode is deposited, current-voltage characteristics test demonstrates that the set threshold voltage is reduced from 13 V to 2.7V and the threshold current from 0.1mA to 0.025mA. Furthermore, we analyse the RIE cleaning principle and compare it with the ultrasonic method.

Highly arsenic-doped Si-on-insulator (SOI) substrate incorporated with buried MoSi2 layers is fabricated aiming at decreasing the collector series resistance of SiGe heterojunction bipolar transistors (HBTs) on SOI, thereby enhancing cutoff frequency (fT) performance and increasing the maximum value of fT (fTMAX). The fT performance at medium current is enhanced and current required for fT = 15 GHz is reduced by half. The value of fTMAX is improved by 30%.

We report the experimental phenomenon of large resistance change in plasma oxidized TiOx/TiNx film fabricated on W bottom-electrode-contact (W-BEC) array. The W-BEC in diameter 260?nm is fabricated by a 0.18??m CMOS technology, and the TiOx/TiNx cell array is formed by rf magnetron sputtering and reactive ion etching. In current?voltage (I?V) measurement for current-sweeping mode, large snap-back of voltage is observed, which indicates that the sample changes from high-resistance state (HRS) to low-resistance state (LRS). In the I?V measurement for voltage-sweeping mode, large current collapse is observed, which indicates that the sample changes from LRS to HRS. The current difference between HRS and LRS is about two orders. The threshold current and voltage for the resistance change is about 5.0?10?5?A and 2.5?V, respectively. The pulse voltage can also change the resistance and the pulse time is as shorter as 30?ns for the resistance change. These properties of TiOx/TiNx film are comparable to that of conventional phase-change material, which makes it possible for RRAM application.

Ge1Sb2Te4-based chalcogenide random access memory array, with a tungsten heating electrode of 260 nm in diameter, is fabricated by 0.18-μm CMOS technology. Electrical performance of the device, as well as physical and electrical properties of Ge1Sb2Te4 thin film, is characterized. SET and RESET programming currents are 1.6 and 4.1 mA, respectively, when pulse width is 100 ns. Both the values are larger than those of the Ge2Sb2Te5-based ones with the same structure and contact size. Endurance up to 106 cycles with a resistance ratio of about 100 has been achieved.

In order to reduce the reset current of chalcogenide random access memory, a W sub-microtube heater electrode with outer/inner diameter of 260/100 nm, which was fabricated with standard 0.18-μm technology, is proposed for the first time to achieve a reset current of about 0.5 mA. The reasons may be that sub-microtube increases the number of electrode edge and thermal efficiency is improved greatly because the thermal density on the edge of sub-microtube electrode is generally the highest.

We investigate the effect of chemicals on chemical mechanical polishing (CMP) of glass substrates. Ceria slurry in an ultra-low concentration of 0.25 wt.% is used and characterized by scanning electron microscopy. Three typical molecules, i.e. acetic acid, citric acid and sodium acrylic polymer, are adopted to investigate the effect on CMP performance in terms of material removal rate (MRR) and surface quality. The addition of sodium acrylic polymer shows the highest MRR as well as the best surface by atomic force microscopy after CMP, while the addition of citric acid shows the worst performance. These results reveal a mechanism that a long-chain molecule without any branches rather than small molecules and common molecules with ramose abundant-electron groups is better for the dispersion of the slurry and thus better for the CMP process.

Phase change memory (PCM) cell array is fabricated by a standard complementary metal–oxide–semiconductor process and the subsequent special fabrication technique. A chalcogenide Ge2Sb2Te5 film in thickness 50 nm deposited by rf magnetron sputtering is used as storage medium for the PCM cell. Large snap-back effect is observed in current–voltage characteristics, indicating the phase transition from an amorphous state (higher resistance state) to the crystalline state (lower resistance state). The resistance of amorphous state is two orders of magnitude larger than that of the crystalline state from the resistance measurement, and the threshold current needed for phase transition of our fabricated PCM cell array is very low (only several μA). An x-ray total dose radiation test is carried out on the PCM cell array and the results show that this kind of PCM cell has excellent total dose radiation tolerance with total dose up to 2×106 rad(Si), which makes it attractive for space-based applications.

A damascene structure of phase change memory (PCM) is fabricated successfully with the chemical mechanical polishing (CMP) method, and the CMP of Ge2Sb2Te5 (GST) and Ti films is investigated. The polished surface of wafer is analysed by scanning electron microscopy (SEM) and an energy dispersive spectrometer (EDS). The measurements show that the damascene device structure of phase change memory is achieved by the CMP process. After the top electrode is deposited, dc sweeping test on PCM reveals that the phase change can be observed. The threshold current of array cells varies between 0.90 mA and 1.15 mA.

We observe reversible phase transition phenomena in proto-type chalcogenide random access memory (C-RAM) devices adopting ultra-thin (12 nm) Ge2Sb2Te5 thin film. In this kind of proto-type device, the ultra-thin amorphous Ge2Sb2Te5 thin film undergoes a crystallization process when a voltage is applied. The polycrystalline Ge2Sb2Te5 remain unchanged when the voltage is below 0.6 V. A higher power is needed if the transition from polycrystalline to amorphous is expected. The re-amorphization process can be realized by applying a voltage higher than 0.7 V. The threshold voltage Vth and threshold electric field Eth of the transition from the polycrystalline state to the amorphous state in this proto-type device are ~0.7 V and ~5×105 V/cm, respectively. The programming voltage is significantly reduced compared to the values of C-RAM devices adopting a 200-nm-thick Ge2Sb2Te5 inset.

We report on the fabrication and characterization of a ZnO-based film-bulk acoustic-resonance device utilized as biosensor. The device has a multilayer structure which consists of piezoelectric element (Au/ZnO/Pt) and a Bragg-reflection-layer acoustic isolation consisting of multilayers of ZnO/Pt. Dielectric measurements have revealed that the device has a very high working frequency (up to ~3.1 GHz), meaning that the device may have a higher sensitivity than the devices reported in the literature.

A single crystal Si thin film on a glass substrate has been obtained successfully by hydrophilic fusion bonding and the smart-cut technology. Tensile strength testing shows that the bonded interface has strong adhesion and the bonding strength is about 8.7 MPa. Crystallinity and microstructure of the samples have been characterized by transmission electron microscopy (TEM). Electrical properties have also been investigated by Hall measurements and four-point probe. The mobility of the transferred Si layer on glass is about 122 cm2/V.s. The results show that the single-crystal silicon layer transferred onto glass by direct bonding keeps good quality for the applications of integrated circuits, transducers, and flat panel display.

A single cell element of chalcogenide random access memory was fabricated by using the focused ion beam method. The contact size between the Ge2Sb2Te5 phase change film and the top electrode film is about 600 nm (diameter) and the contact area is calculated to be 0.28 μm2. The thickness of the phase change film is 83 nm. The current–voltage characteristics of the cell element are studied using the home-made current–voltage tester in our laboratory. The minimum threshold current of about 0.6 mA is obtained.

Annealing temperature effects on the structure and electrical resistance of Ge2Sb2Te5 thin film were studied. The crystallization and melting temperature of the thin film are about 175 degrees C and 610 degrees C respectively. The structure of the as-deposited and the annealed film at different annealing temperatures are identified by the x-ray diffraction method. The thin film changes from an amorphous state to the fcc structure at about 200 degrees C, and then changes into the hexagonal close-packed (hcp) structure at about 400 degrees C. Electrical resistance of as-deposited thin film reaches as high as 1.7×108 Ω/sq. Then it decreases to 1.6×104 Ω/sq and 165 Ω/sq after the annealing process at 250 degrees C and 400 degrees C respectively. The current–voltage curve of the Ge2Sb2Te5 thin film is also investigated. Due to the large resistance difference between the amorphous, the fcc crystalline and the hcp crystalline states, Ge2Sb2Te5 film may be used to realize multilevel storage for Ovonic unified memory.

Zirconium oxide films were deposited on p-type Si(100) substrates using high vacuum electron beam evaporation (HVEBE) at room temperature. X-ray photoelectric spectroscopy shows that the dominant chemical state of zirconia thin films is in the fully oxidized state of Zr4+, no matter whether annealed in oxygen. The structural information from x-ray diffraction shows that zirconia thin films deposited at room temperature by HVEBE were completely amorphous before and after the annealing. The spreading resistance profile indicates that ZrO2 thin films have excellent insulation property (with a resistance of more than 108 Ω) and the thickness is 800 A. After thermal treatment at 600°C in O2 ambient, the root-mean-square roughness changed from 8.09 A of the as-deposited film to 13.8 A across an area of 1×1 µm2.

A Ge2Sb2Te5 based phase change memory device cell integrated with metal-oxide semiconductor field effect transistor (MOSFET) is fabricated using standard 0. 18 μm complementary metal-oxide semiconductor process technology. It shows steady switching characteristics in the dc current-voltage measurement. The phase changing phenomenon from crystalline state to amorphous state with a voltage pulse altitude of 2.0 V and pulse width of 50 ns is also obtained. These results show the feasibility of integrating phase change memory cell with MOSFET.

A phase change memory (PCM) device, based on the Ge2Sb2Te5 (GST) material, is fabricated using the standard 0.18-μm CMOS technology. After serials of detailed experiments on the phase transition behaviors, we find that the RESET process is strongly dependent on the state of the inactive area and the active area affects the SET process dramatically. By applying a 5-mA current-voltage (I — V) sweep as initial operation, we can reduce the voltage drop beyond the active area during the RESET process and the overall RESET voltage decreases from 3 V plus to 2.5 V. For the SET operation, a non-cumulative programming method is introduced to eliminate the impact of randomly formed amorphous active area, which is strongly related to the threshold switching process and SET voltage. Combining the two methods, the endurance performance of the PCM device has been remarkably improved beyond 1 × 106 cycles.

Novel Si3.5Sb2Te3 phase change material for phase change memory is prepared by sputtering of Si and Sb2Te3 alloy targets. Crystalline Si3.5Sb2Te3 is a stable composite material consisting of amorphous Si and crystalline Sb2Te3, without separated Te phase. The thermally stable Si3.5Sb2Te3 material has data retention ability (10 years at 412K) better than that of the Ge2Sb2Te5 material (10 years at 383 K). Phase change memory device based on Si3.5Sb2Te3 is successfully fabricated, showing low power consumption. Up to 2.2 × 107 cycles of endurance have been achieved with a resistance ratio lager than 300.

Simulation of the heat consumption in phase change random access memories (PCRAMs) is investigated by a three-dimensional finite element model. It is revealed that the thermal conductivity and electrical conductivity of the buffer layer are crucial in controlling the heating efficiency in RESET process. The buffer layer materials W, TiN, WO3, TiO2 and poly-germanium (poly-Ge) are applied in the simulation respectively, and compared with each other. The simulation results show that limitation of electrical conductivity is effective on heating efficiency and the limitation of thermal conductivity is important on the reliable RESET process.

A three-dimensional finite element model for phase change random access memory (PCRAM) is established for comprehensive electrical and thermal analysis during SET operation. The SET behaviours of the heater addition structure (HS) and the ring-type contact in bottom electrode (RIB) structure are compared with each other. There are two ways to reduce the RESET current, applying a high resistivity interfacial layer and building a new device structure. The simulation results indicate that the variation of SET current with different power reduction ways is little. This study takes the RESET and SET operation current into consideration, showing that the RIB structure PCRAM cell is suitable for future devices with high heat efficiency and high-density, due to its high heat efficiency in RESET operation.

A thin TiO2 layer inserted in a phase change memory (PCM) cell to form a deep sub-micro bottom electrode (DBE) is proposed and its electro-thermal characteristics are investigated with the three-dimensional finite element analysis. Compared with the conventional PCM cell with a SiN stop layer, the reset threshold current of the PCM cell with the TiO2 layer is reduced from 1.8 mA to 1.2 mA and the ratio of the amorphous resistance and crystalline resistive increases from 65 to 100. The optimum thickness of the TiO2 layer and the optimum height of DBE are 10 nm and 200 nm, respectively. Therefore, the PCM cell with the TiO2 layer can decrease the programming power consumption and increase heating efficiency. The TiO2 film is a better candidate for the SiN film in the PCM cell structure to prepare DBE and to reduce programming power in the reset operation.

Phase change random access memory (PC-RAM) based on Si2Sb2Te5 with a Pt tapered heating electrode (Pt-THE), which is fabricated using a focus ion beam (FIB), is investigated. Compared with the tungsten electrode, the Pt-THE facilitates the temperature rise in phase change material, which causes the decrease of reset voltage from 3.6 to 2.7 V. The programming region of the cell with the Pt-THE is smaller than that of the cell with a cylindrical tungsten heating electrode. The improved performance of the PC-RAM with a Pt-THE is attributed to the higher resistivity and lower thermal conductivity of the Pt electrode, and the reduction of the programming region, which is also verified by thermal simulation.

Based on the temperature dependence of the Arrhenius law, an HSPICE compact module using Verilog-A language for phase change memory (PCM) is presented. In the model of this HSPICE compact module, the basic theory that the resistance of the amorphous semiconductor has relations with the activation energy and temperature is used, and an assumption that this theory can be expanded to describe the crystalline semiconductor is employed. Moreover, since an objective reality that the resistance of the semiconductor determines the temperature and the temperature affects the resistance inversely is inevitable, coupling with such positive feedback, this model can reproduce the real-time characteristics of the memory cell accurately. The simulation results show that this model can reproduce the features of the PCM cell well. It can be used in the PCM circuit design and further analysis.

Ultra-thin and near-fully relaxed SiGe substrate is fabricated using a modified Ge condensation technique, and then a 25-nm-thick biaxially tensile strained-Si with a low rms roughness is epitaxially deposited on a SiGeon-Insulator (SGOI) substrate by ultra high vacuum chemical vapor deposition (UHVCVD). High-Resolution cross-sectional transmission electron microscope (HR-XTEM) observations reveal that the strained-Si/SiGe layer is dislocation-free and the atoms at the interface are well aligned. Furthermore, secondary ion mass spectrometry (SIMS) results show a sharp interface between layers and a uniform distribution of Ge in the SiGe layer. One percent in-plane tensile strain in the strained-Si layer is confirmed by ultraviolet (UV) Raman spectra, and the stress maintained even after a 30-s rapid thermal annealing (RTA) process at 1000°C According to those results, devices based on strained-Si are expected to have a better performance than the conventional ones.