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10-kV 4H–SiC p-channel insulated gate bipolar transistors (IGBTs) are designed, fabricated, and characterized in this paper. The IGBTs have an active area of 2.25 mm2 with a die size of 3 mm × 3 mm. A step space modulated junction termination extension (SSM-JTE) structure is introduced and fabricated to improve the blocking performance of the IGBTs. The SiC p-channel IGBTs with SSM-JTE termination exhibit a leakage current of only 50 nA at −10 kV. To improve the on-state characteristics of SiC IGBTs, the hexagonal cell (H-cell) structure is designed and compared with the conventional interdigital cell (I-cell) structure. At an on-state current of 50 A/cm2, the voltage drops of I-cell IGBT and H-cell IGBT are 10.1 V and 8.3 V respectively. Meanwhile, on the assumption that the package power density is 300 W/cm2, the maximum permissible current densities of the I-cell IGBT and H-cell IGBT are determined to be 34.2 A/cm2 and 38.9 A/cm2 with forward voltage drops of 8.8 V and 7.8 V, respectively. The differential specific on-resistance of I-cell structure and H-cell structure IGBT are and , respectively. These results demonstrate that H-cell structure silicon carbide IGBT with SSM-JTE is a promising candidate for high power applications. [ABSTRACT FROM AUTHOR]

The interface properties and electrical characteristics of the n-type 4H–SiC planar and trench metal–oxide–semiconductor (MOS) capacitors are investigated by measuring the capacitance voltage and current voltage. The flat-band voltage and interface state density are evaluated by the quasi-static method. It is not effective on further improving the interface properties annealing at 1250°C in NO ambient for above 1 h due to the increasing interface shallow and fast states. These shallow states reduce the effective positive fixed charge density in the oxide. For the vertical MOS capacitors on the () and () faces, the interface state density can be reduced by approximately one order of magnitude, in comparison to the result of the planar MOS capacitors on the (0001) face under the same NO annealing condition. In addition, it is found that Fowler–Nordheim tunneling current occurs at an oxide electric field of 7 MV/cm for the planar MOS device. However, Poole–Frenkel conduction current occurs at a lower electric field of 4 MV/cm for the trench MOS capacitor. This is due to the local field crowded at the trench corner severely causing the electrons to be early captured at or emitted from the SiO2/SiC interface. These results provide a reference for an in-depth understanding of the mobility-limiting factors and long term reliability of the trench and planar SiO2/SiC interfaces. [ABSTRACT FROM AUTHOR]