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The physical implementation of artificial neural networks, also known as “neuromorphic engineering” as advocated by Carver Mead in the late 1980s, has become urgent because of the increasing demand on massive and unstructured data processing. complementary metal-oxide-semiconductor-based hardware suffers from high power consumption due to the von Neumann bottleneck; therefore, alternative hardware architectures and devices meeting the energy efficiency requirements are being extensively investigated for neuromorphic computing. Among the emerging neuromorphic electronics, oxide-based three-terminal artificial synapses merit the features of scalability and compatibility with the silicon technology as well as the concurrent signal transmitting-and-learning. In this Perspective, we survey four types of three-terminal artificial synapses classified by their operation mechanisms, including the oxide electrolyte-gated transistor, ion-doped oxide electrolyte-gated transistor, ferroelectric-gated transistor, and charge trapping-gated transistor. The synaptic functions mimicked by these devices are analyzed based on the tunability of the channel conductance correlated with the charge relocation and polarization in gate dielectrics. Finally, the opportunities and challenges of implementing oxide-based three-terminal artificial synapses in physical neural networks are delineated for future prospects.

Gradual switching in the memristor or memcapacitor devices is the key parameter for the next generation of bio-inspired neuromorphic computing. Here, we have fabricated the WOx/ZrOx dual-oxide layered device, which shows the coexistence of gradual resistive and capacitive switching arisen from the current and capacitance hysteresis curves, respectively. The expansion of hysteresis loop can be modulated by altering the oxygen content in the oxide materials. Interestingly, the presence of negative differential resistance (NDR) is dependent on the voltage sweep direction and range of applied bias, which can be reasoned by the local electric field, charge trapping/detrapping, and conduction band offset at the dual-oxide interface. This study provides the concept of the coexistence of current and capacitance hysteresis along with NDR, and it is highly potential for memristor and memcapacitor circuits to explore neuromorphic computing.

An edge-free structure and hermetic encapsulation technique are presented that enable SiOx-based resistive random-access memory (RRAM) operation in air. A controlled etch study indicates that the switching filament is close to the SiOx surface in devices with an exposed SiOx edge. Electrical test of encapsulated, edge-free devices in 1 atmosphere air indicates stable switching characteristics, unlike devices with an edge. This work demonstrates that SiOx RRAM is able to operate in air with proper encapsulation and an edge-free structure. The resistive switching failure mechanism when operating in air is explained by the oxidation of hydrogen-complexed defects in the switching filament.

Split-ring resonators (SRRs) have been the subject of investigation as plasmonic sensors that operate by sensing plasmon resonance shift δλ when exposed to a medium with a refractive index change δn. However, conventional planar SRRs have their plasmon fields spread into the substrates, reducing accessible sensing volume and its sensing performance. Such a limitation can be eradicated with vertical SRRs in which the plasmon fields localized in SRR gaps are lifted off from the substrate, allowing for greatly enhanced sensitivity. Here, we demonstrate the highest sensitivity among reported SRR-based sensors in optical frequencies.

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

We demonstrate a facile annealing method to improve the polymer chain ordering of poly(3-hexythiophene) (P3HT):fullerene blend triggered by a small amount of FePt nanowires (FePt NWs). By applying a magnetic field perpendicular to the substrate during the solvent drying process, the resulting P3HT:fullerene:FePt NWs film becomes highly optical anisotropy and exhibits a much stronger X-ray diffraction intensity of P3HT. We hypothesize that the coupling force between the FePt NWs and P3HT can assist the polymer chain alignment leading to an improved device performance. The proposed approach is simple and can be applied to other polymer blend systems as well.

The electroforming voltages (Vef) of silicon oxide resistive random access memory devices with oxide sidewall etched to different degrees are compared. The results show that the Vef is significantly reduced when more sidewall area is formed, and Vef of around 17 V is achieved in devices with maximum sidewall area. Plausible electroforming and state switching mechanisms are discussed using a filament-gap model. Endurance measurements up to 107 pulse cycles are compared for different device types. An external series resistance may be helpful for decreasing voltage stress during pulsed cycling to help enable device survival beyond 107 pulse cycles.

Nucleation mechanism of catalyst-free GaN nanorod grown on Si(111) is investigated by the fabrication of uniform and narrow (andlt; 35 nm) nanorods without a pre-defined mask by molecular beam epitaxy. Direct evidences show that the nucleation of GaN nanorods stems from the sidewall of the underlying islands down to the Si(111) substrate, different from commonly reported ones on top of the island directly. Accordingly, the growth and density control of the nanorods is exploited by a "narrow-pass" approach that only narrow nanorod can be grown. The optimal size of surrounding non-nucleation area around single nanorod is estimated as 88 nm. Funding Agencies|Academia Sinica and National Science Council in Taiwan||Swedish Foundation for Strategic Research (SSF) in Sweden, KA Wallenberg||MEXT through Grant-in-Aids for Scientific Research (A) in Japan|21246004

At modest laser powers (∼1 kW/cm2) ceramic Pb(Mg0.3Nb0.6Ti0.09)O3 exhibits optical bistability. The mechanism is shown to be thermal focusing. At power densities ∼1 kW/cm2 the oscillations between metastable states become nearly periodic (∼8 Hz), in analogy with the behavior exhibited in thermotropic liquid films [M. V. Vasnetsov, JETP Lett. 50, 480 (1990)]. At lower power levels (0.5 kW/cm2) aperiodic switching events are observed with one event per 45 mW (35 W/cm2) of increased laser power, with the Nth switching event occurring at time tN=AN(P−PN)−1, where P is the incident laser power and AN and PN are constants independent of P. The switching events depend also strongly on specimen temperature and its surrounding air pressure.

In this study, the resistance switching characteristics of a resistive random access memory device with Pt/InOx/TiN structure is investigated. Unstable bipolar switching behavior is observed during the initial switching cycle, which then stabilizes after several switching cycles. Analyses indicate that the current conduction mechanism in the resistance state is dominated by Ohmic conduction. The decrease in electrical conductance can be attributed to the reduction of the cross-sectional area of the conduction path. Furthermore, the device exhibits low operation voltage and power consumption.

In this study, a Pt/BiFeO3/TiN device was fabricated and the resistance switching characteristics were investigated. After the first forming process, the conduction path was formed and exhibited unstable bipolar switching characteristics. Subsequently, the original conduction path was destroyed thoroughly by high negative bias. By reconstructing the conduction path after a second forming process (re-forming process), the device exhibits stable bipolar switching characteristics. Transmission electron microscopy analysis indicates that the stability of switching behavior was enhanced because of the joule heating effect, and is an easy way to improve the resistance switching characteristics.

The ZnO-SiO2 nanocomposite solar-blind metal-semiconductor-metal photodetectors (PDs) on flexible polyethersulfone (PES) with an organosilicon (SiOx(CH3)) buffer layer improved the −10 V-biased responsivity of PDs illuminated wavelength of 240 nm from 0.75 A/W (without SiOx(CH3) buffer layer) to 3.86 A/W and the deep-ultraviolet (DUV)–visible rejection ratio of PDs from 8.10 × 104 (without SiOx(CH3) buffer layer) to 1.75 × 105. Moreover, the inserted SiOx(CH3) buffer layer would reduce the responsivity and DUV-visible rejection ratio of degradation of the severely bended ZnO-SiO2 nanocomposite PDs on PES.

This report compares Mo-doped and undoped SiO2 thin films of a similar thickness as well as MoOx. The Mo-doped SiO2 film exhibited switching behavior after the forming process, unlike the undoped SiO2 film. Through material analyses, a self-assembled layer is observed in the Mo-doped SiO2 film. Due to the formation of this layer, the thickness required to be broken down is effectively reduced. Subsequently, the occurrence of the switching behavior in the thinner SiO2 film further confirmed the supposition. A comparison of the two switching behaviors shows that SiO2 dominates the switching characteristic of the Mo-doped SiO2.

The electroforming voltage (Vef) of silicon oxide resistive random access memories treated with post-deposition-anneal (PDA) and/or post-metal-anneal in different gas ambients is compared. Secondary ion mass spectroscopy result shows significant incorporation of H/D atoms in SiOx after anneals in H2/N2 and D2/N2. Vef is significantly reduced after anneal in H2/N2 or D2/N2, but D2/N2 anneal results in even lower Vef, which could be due to more stable Si passivation in the Si-D/O+ pair as compared to the Si-H/O+ pair. On and off state currents are measured at 200 mV gate bias every 60 s for a total time of 6000 s with results showing good data retention for both on and off states. On and off state currents are observed to decrease when using PDA resulting in lower overall power dissipation.

The multiple micro/nano-patterning on p-GaN surface by femtosecond (fs) laser irradiation through a micro-ball lens array (MBLA) mask has been established to improve the light extraction efficiency of GaN-based light-emitting diodes (LEDs). This technique was meant for the high-speed surface micro/nano-patterning of a p-GaN surface on a large area using fs laser irradiation. Compared with conventional LEDs with flat surfaces, dual-scale roughened structures on p-GaN surface LEDs used in the present experiment scatter and increase the effective critical angle, increasing the escape probability of photons. The relationship of the hole size on p-GaN surface and the refractive index of the MBLA material would be also discussed. With an injection current of 20 mA, the output power of the experimental LEDs markedly improved by a magnitude of 48% compared with conventional GaN-based LEDs.

The normalized gains, which determines the intrinsic photoconduction (PC) efficiencies, have been defined and compared for the gallium nitride (GaN) nanowires (NWs) grown by chemical vapor deposition (CVD) and molecular beam epitaxy (MBE). By excluding the contributions of experimental parameters and under the same light intensity, the CVD-grown GaN NWs exhibit the normalized gain which is near two orders of magnitude higher than that of the MBE-ones. The temperature-dependent time-resolved photocurrent measurement further indicates that the higher photoconduction efficiency in the CVD-GaN NWs is originated from the longer carrier lifetime induced by the higher barrier height (ϕB = 160 ± 30 mV) of surface band bending. In addition, the experimentally estimated barrier height at 20 ± 2 mV for the MBE-GaN NWs, which is much lower than the theoretical value, is inferred to be resulted from the lower density of charged surface states on the non-polar side walls.

The effects of SF6 plasma treatment of Al2O3 on InP substrate have been investigated in this paper. Electrical characteristics including drive current, effective channel mobility, transconductance, subthreshold swings, etc., have been compared for devices with SF6 plasma treatment at different power (P = 30 or 50 W) for different time (t = 3, 5, or 7 min). With 5 min SF6 plasma treatment at power = 30 W, the maximum drive current is increased by 20% to 60.2 μA/μm and effective channel mobility is increased by 36.7% to 1099 cm2/V s for devices on InP substrate with 7 nm Al2O3 (EOT ∼ 3.4 nm and W/L = 600 μm/10 μm). It is believed S and F atoms are incorporated into Al2O3 bulk and Al2O3/InP interface, so that better oxide quality and a lower interface trap density are achieved by SF6 plasma treatment at optimal power with optimal time duration.

The SiOx-based resistive switching memory was realized by a simple TaN/SiO2/n++ Si-substrate structure. Post-deposition annealing treatment not only reduced operational variation but also stabilized electrical reliability during repeated switching. The relationship between applied voltage polarity and reset switching parameters is investigated and may indicate that resistive switching occurs at the cathode side. Oxygen-vacancy clustering and asymmetrical thermal-dissipation of the electrodes are discussed as possible causes for the polarity dependence of reset switching parameters. Data retention in high- and low-resistance states was measured for over 104 s, indicating promising potential for future nonvolatile memory applications.

In this work, we demonstrate that device characteristics could be significantly improved by incorporating more fluorine (F) into HfO2 dielectrics layer using low power SF6 plasma treatment at different positions of gate oxide. Fluorine was incorporated in three ways: 4 min treatment from the top of 6 nm HfO2, 4 min treatment in the middle of 6 nm HfO2, or 2 min treatment each in the middle and from the top of HfO2 layer. Drive current (Id) and effective channel mobility could be improved by 70% and 51%, respectively, for devices with treatment both in the middle and from the top of HfO2 high κ layer compared to those of devices without SF6 treatment. The impact of SF6 plasma treatment on devices with HfO2/In0.53Ga0.47As stack is also presented.

The resistive switching between high impedance (“off” state) and low impedance (“on” state) is demonstrated on e-beam evaporated SiOx/Si resistive random access memory devices in this paper. The set and reset voltages are independent of the device perimeters and oxide thicknesses after electroforming. A circuit model including filament conductance G is proposed to explain the measured “on” state capacitances under frequency ranges from 1 KHz to 1 MHz. The electrochemical redox process is adopted to explain the formation of Si filament during electroforming and switching. “On” and “off” currents were also measured at various operating temperatures. It is found that both set and reset voltages increase as temperature decreases and that no electroforming is exhibited at low temperature T = 77 K.

This paper investigates the improvement of resistive switching trends after post-forming negative bias stress treatment of a Pt/Yb2O3/TiN device that has undergone positive bias forming process for activation. After the treatment, characteristics of the conductive filament, such as the temperature dependence of resistivity and transition mechanism, undergo changes. Furthermore, this treatment causes the conductive filament to transform from being primarily composed of vacancies to being metallic Yb dominant, which not only reduces operation voltages such as Vset and Vreset but also improves the on/off ratio. In reliability tests, the device has stable retention.

The functionalization of graphene oxide (GO) sheets with polyimide (PI) enables the layer-by-layer fabrication of a GO-PI hybrid resistive-switch device and leads to high reproducibility of the memory effect. The current-voltage curves for the as-fabricated device exhibit multilevel resistive-switch properties under various reset voltages. The capacitance-voltage characteristics for a capacitor based on GO-PI nanocomposite indicate that the electrical switching may originate from the charge trapping in GO sheets. The high device-to-device uniformity and unique memory properties of the device make it an attractive candidate for applications in next-generation high-density nonvolatile flash memories.

Improved device performance of InGaAs channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been achieved by utilizing InP and InAlAs barrier layer. In0.7Ga0.3As buried-channel MOSFETs with various InP barrier thicknesses and InP/InAlAs double barrier have been fabricated and compared in terms of performances parameters such as drive current, transconductance, subthreshold swing (SS), and effective mobility. Devices with 1 nm InP barrier exhibits 59% increase in drive current and 65% increase in peak effective channel mobility compared to devices without barrier layer. With thicker barrier, devices show higher drive current and higher mobility. Devices with InP/InAlAs double barrier exhibit the highest effective channel mobility.

We demonstrate a concept of optical data storage through plasmonic resonances of metallic nanostructures. Metallic nanostructures exhibit strong variations in their reflectance and/or transmittance spectra due to surface plasmon polariton resonances. We study the variations in spectra through 50×50 arrays of repeated unit cells covering a total area of ∼50×50 μm2. Each cell contains ten different nanofeatures, such as an ellipse, a ring, a circle, a triangle, a square, etc. The size of each unit-cell is 500×500 nm2, and the periodicity is 1.0 μm. The variations in spectra are obvious enough to be distinguished and then retrieved.

We have compared the device performance of In0.7Ga0.3As HfO2 gate dielectric tunneling field-effect-transistors (TFETs) using p++/i or p++/n+ tunneling junctions. Devices with p++/n+ tunneling junctions show 61% and 20% higher current at Vg-Vth=0.5 and 2 V compared to the ones with p++/i junctions. These p++/n+ TFETs exhibit an on-current of 60 μA/μm and a minimum subthreshold swing of 84 mV/dec. Device characteristics of TFETs using p++/n+ tunneling diodes with various n+ region doping concentrations have been simulated, results indicate the doping concentration of the n+ region plays an important role in determining the on-current and providing a well gate-controlled tunneling behavior.

Performance improvement of InGaAs buried channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been achieved by inserting InAs layer and properly designing the inserted layer position. In0.7Ga0.3As and InAs channel buried channel MOSFETs were fabricated and analyzed including drive current, transconductance, effective mobility, and subthreshold swing. All InAs buried channel devices show good off-state and saturation property. By inserting InAs in the middle of InGaAs channel (InGaAs/InAs/InGaAs channel), 37% enhancement of high field effective channel mobility was achieved over devices with pure InGaAs channel. Devices with InAs inserted in the middle exhibits peak effective channel mobility around 6140 cm2/V s and subthreshold swing of 107 mV/dec.

In this work, the experimental impact of SF6 plasma treatment on the performance of InP metal-oxide-semiconductor field-effect transistors is presented. S and F are incorporated into atomic layer deposited HfO2 via postgate SF6 plasma treatment. The decreased subthreshold swing, gate leakage (Ig), and increased effective channel mobility (μeff) indicate that better interface and bulk oxide quality have been achieved with SF6 plasma treatment due to the formation of stronger Hf–F bonds. Drive current (Id), transconductance (Gm), and effective channel mobility (μeff) are improved by 22.3%, 35%, and 35%, respectively, compared with those of control devices.

The NiSi2/SiNx compound nanocrystals (CNCs) were fabricated to integrate the compound tunnel barrier into nanocrystal memory, with the inclusion of nitride traps. The analysis of high resolution transmission electron microscopy and x-ray photoelectron spectroscopy reveal that the nanocrystal is mainly composed of NiSi2 and silicon nitride with small size of 4–5 nm and high density of ∼1×1012 cm−2. The charge storage characteristics of the memory capacitor based on NiSi2/SiNx CNCs were investigated by capacitance-voltage measurement and the enhanced retention characteristics, which remain 71.7% (∼1.9 V) in 104 s, are clarified to be due to the compound tunnel barrier and traps in nitride.

In this work, the effects of fluorine (F) incorporation on electrical characteristics of HfO2/InP and HfO2/In0.53Ga0.47As gate stack are presented. F had been introduced into HfO2 gate dielectric by postgate CF4 plasma treatment, which was confirmed by x-ray photoelectron spectroscopy analysis and a secondary ion mass spectrometry technique. Compared to the control sample, fluorinated samples had great improvements in subthreshold swing, hysteresis, the normalized extrinsic transconductance, and the normalized drain current. These improvements can be attributed to the reduction in fixed charge in the HfO2 bulk and less interface trap density at the HfO2/III–V interface.

We have applied single InP barrier layer with different thicknesses and InP/In0.52Al0.48As double-barrier layer to In0.7Ga0.3As Al2O3 metal-oxide-semiconductor field-effect-transistors (MOSFETs) and investigated their effects on device performance. In0.7Ga0.3As MOSFETs with 3 nm InP single-barrier attain 22% higher peak effective mobility while devices with 5 nm InP attain 58% higher peak mobility than the ones without barrier. Devices using InP/In0.52Al0.48As double-barrier achieve mobility enhancement at both low-field (68% at peak mobility) and high-field (55%) compared to ones without barrier. High channel mobility of 4729 cm2/V s has been obtained using InP/In0.52Al0.48As barrier and atomic-layer-deposited Al2O3 gate oxide.

In this work, we demonstrate that the electrical performance of HfO2/In0.53Ga0.47As gate stack can be greatly improved by incorporating fluorine (F) and engineering its concentration depth profile with respect to HfO2 bulk and the HfO2/In0.53Ga0.47As interface. We introduce F into gate stacks in two ways: CF4 plasma treatment has been performed after 8 nm HfO2 deposition or after partial deposition of HfO2 4 nm and followed by 4 nm HfO2 deposition to make the overall thickness 8 nm. The latter one incorporates more F into the HfO2 and shows great improvements. Fluorine is believed to reduce fixed charge by forming Hf–F bonds in the HfO2 bulk and also passivate the interface traps in the HfO2/In0.53Ga0.47As interface.

We have investigated the effects of gate-first and gate-last process on oxide/InGaAs interface quality using In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOSCAPs) with atomic-layer-deposited (ALD) oxides. Sequence of source/drain activation anneal in the process results in remarkable electrical and physical difference. Applying gate-last process provides significant frequency dispersion reduction and interface trap density reduction for InGaAs MOSCAPs compared to gate-first process. A large amount of In–O, Ga–O, and As–As bonds was observed on InGaAs surface after gate-first process while no detectable interface reaction after gate-last process. Electrical and physical results also show that ALD Al2O3 exhibits better interface quality on InGaAs than HfO2.

The InGaN-based light-emitting diodes (LEDs) with a roughened patterned backside on the N-face GaN surface were fabricated through a crystallographic etching process to increase light-extraction efficiency. After laser decomposition, laser scribing, and a lateral crystallographic wet etching process at the GaN/Al2O3 interface, stable crystallographic etching planes were formed as the GaN {1011¯} planes that included an angle with the top GaN (0001) plane measured at 58°. The GaN buffer layer acted as the sacrificial layer for the laser decomposition process and the lateral wet etching process with a 26 μm/min etching rate. The LED with the inverted pyramidal N-face GaN surface close to the GaN/Al2O3 interface has a larger light-scattering process than the conventional LED. The light-output power of the LED with the backside roughened surface had a 47% enhancement when measured in LED chip form.

In this work, a postgate CF4 plasma treatment has been demonstrated on In0.53Ga0.47As channel metal-oxide-semiconductor field-effect transistors. Fluorine (F) has been incorporated into the atomic layer deposited Al2O3 gate dielectric by postgate CF4 plasma treatment. A smaller subthreshold swing and reduced interface trap density has been achieved with F passivation, suggesting a better interface quality. With CF4 plasma treatment, drive current, transconductance and effective channel mobility has been shown to increase by 13.9%, 12.5%, and 29.6%, in comparison to the control devices, respectively.

In this letter, we demonstrate the electrical properties of metal-oxide-semiconductor capacitors and metal-oxide-semiconductor field-effect transistors (MOSFETs) on InP using atomic layer deposited HfO2 gate dielectric and a thin silicon interface passivation layer (Si IPL). Compared with single HfO2, the use of Si IPL results in better interface quality with InP substrate, as illustrated by smaller frequency dispersion and reduced hysteresis. MOSFETs with Si IPL show much higher drive current and transconductance, improved subthreshold swing, interface-trap density and gate leakage current with equivalent oxide thickness scaling down to 18 A.

We have investigated device performance for In0.7Ga0.3As and In0.53Ga0.47As metal-oxide-semiconductor transistors (MOSFETs) with and without InP barrier layer using atomic layer deposited Al2O3 gate dielectric. InP barrier layer was found to provide higher transconductance for both In0.7Ga0.3As and In0.53Ga0.47As MOSFETs, especially for In0.7Ga0.3As. In0.7Ga0.3As MOSFETs with InP barrier layer show much higher transconductance and lower subthreshold swing than other MOSFETs studied. These In0.7Ga0.3As MOSFETs exhibit high drive current of 98 mA/mm (L=20 μm), subthreshold swing of 106 mV/decade and maximum effective channel mobility of 4402 cm2/V s.

We have investigated the channel doping concentration and channel thickness dependence of device performance for In0.53Ga0.47As metal-oxide-semiconductor transistors with atomic layer deposited Al2O3 dielectrics. We found that undoped channel provides the highest drive current of 125 mA/mm for 5 μm gate length. With proper substrate doping concentration (5×1016/cm3), reasonable subthreshold swing (104 mV/decade) can be achieved for 4.7 nm equivalent oxide thickness. Thinner InGaAs channel exhibits lowest off-current density of 4.0×10−6 mA/mm.

InGaN-based light emitting diodes (LEDs) with a top pattern-nanoporous p-type GaN:Mg surface were fabricated by using a photoelectrochemical (PEC) process. The peak wavelengths of electroluminescence (EL) and operating voltages were measured as 461.2 nm (3.1 V), 459.6 nm (9.2 V), and 460.1 nm (3.3 V) for conventional, nanoporous, and pattern-nanoporous LEDs using 20 mA operation current. The EL spectrum of the nanoporous LED had a larger blueshift phenomenon as a result of a partial compression strain release in the InGaN active layer through the formation of a top nanoporous surface. The light output power had 12.1% and 26.4% enhancements for the nanoporous and the pattern-nanoporous LEDs compared with conventional LEDs. The larger operating voltage of the nanoporous LED was due to the non-ohmic contact on the PEC treated p-type GaN:Mg surface. By using a pattern-nanoporous p-type GaN:Mg structure, the operating voltage of the pattern-nanoporous LED was reduced to 3.3 V. A lower compression strain in the InGaN active layer and a higher light extraction efficiency at the top nanoporous surface were observed in pattern-nanoporous LEDs for higher efficiency nitride-based LED applications.

In this paper, location-controlled silicon crystal grains are fabricated by the excimer laser crystallization method which employs amorphous silicon spacer structure and prepatterned thin films. The amorphous silicon spacer in nanometer-sized width formed using spacer technology is served as seed crystal to artificially control superlateral growth phenomenon during excimer laser irradiation. An array of 1.8-μm-sized disklike silicon grains is formed, and the n-channel thin-film transistors whose channels located inside the artificially-controlled crystal grains exhibit higher performance of field-effect-mobility reaching 308cm2∕Vs as compared with the conventional ones. This position-manipulated silicon grains are essential to high-performance and good uniformity devices.