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In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-gm), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si3N4, Rapid Thermal Chemical Vapor Deposition Si3N4, and Atomic Layer Deposition (ALD) Al2O3) for AlGaN/GaN Metal-Insulator- Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (Dit), the amount of border traps, and the threshold voltage (VTH) shift during a positive gate bias stress can be obtained. The results show that the VTH shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the VTH shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract Dit needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the gm dispersion commonly attributed to border traps might be influenced by interface states. [ABSTRACT FROM AUTHOR]

Low barriers for electrons are found to be the reason for significant charge instability at interfaces of (100)InP and (100)In0.53Ga0.47As with atomic-layer deposited TaSiOx insulators. The formation of these reduced barriers is associated with the growth of a narrow-bandgap interlayer between the semiconductor and TaSiOx, which enables electron tunneling at low electric fields and subsequent trapping in the insulator. A wide-gap passivation layer may be required to improve the performance of TaSiOx as gate insulator. [ABSTRACT FROM AUTHOR]

Energy barriers at interfaces of (100)InP with atomic-layer deposited Al2O3 are determined using internal photoemission of electrons. The barrier height between the top of the InP valence band and bottom of the alumina conduction band is found to be 4.05±0.10 eV corresponding to a conduction band offset of 2.7 eV. An interlayer associated with the oxidation of InP may result in a lower barrier for electron injection potentially leading to charge instability of the insulating stack. A wide-gap P-rich interlayer has a potential to reduce this degrading effect as compared to In-rich oxides. [ABSTRACT FROM AUTHOR]

The authors model the capacitance-voltage (CV) behavior of In0.53Ga0.47As metal-oxide-semiconductor (MOS) structures and compare the results to experimental CV-curves. Due to the very low conduction band density of states, ideal III-V MOS structures should present an asymmetric CV behavior, with lower accumulation capacitance on the conduction band side. The absence of this asymmetric CV shape in experimental CV curves points toward the presence of additional states inside the conduction band at the oxide-semiconductor interface. Comparisons between the model and experimental data allow the determination and approximate quantification of a large acceptorlike interface state density above the conduction band edge energy. [ABSTRACT FROM AUTHOR]

Room-temperature photoreflectance is employed to investigate the Fermi level pinning and surface state density of a GaAs0.65Sb0.35 surface intrinsic-n+ (SIN+) structure. Based on the thermionic emission theory and current-transport theory, the surface Fermi level VF and surface state density are determined experimentally from the dependence of the surface barrier height on the pump beam intensity. The surface state density Ds is estimated as approximately 1.91×1013 cm-2, and the Fermi level is located 0.63 eV below the conduction band edge at the surface. By sequential etching of the intrinsic layer, the Fermi level pinning in GaAs0.65Sb0.35 SIN+ structure is further demonstrated. [ABSTRACT FROM AUTHOR]

The authors apply the conductance method at 25 and 150 °C to GaAs–Al2O3 metal-oxide-semiconductor devices in order to derive the interface state distribution (Dit) as a function of energy in the bandgap. The Dit is governed by two large interface state peaks at midgap energies, in agreement with the unified defect model. S-passivation and forming gas annealing reduce the Dit in large parts of the bandgap, mainly close to the valence band, reducing noticeably the room temperature frequency dispersion. However the midgap interface state peaks are not affected by these treatments, such that Fermi level pinning at midgap energies remains. [ABSTRACT FROM AUTHOR]

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263 mA/mm are obtained for 1 μm gate-length Al2O3 MOS-HEMTs with 3 and 6 nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3–5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ∼3×103 with a subthreshold swing of 90 mV/decade. A maximum cutoff frequency (fT) of 27.3 GHz and maximum oscillation frequency (fmax) of 39.9 GHz and an effective channel mobility of 4250 cm2/V s are measured for the 1 μm gate-length Al2O3 MOS-HEMT with 6 nm gate oxide. Hooge’s constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device. [ABSTRACT FROM AUTHOR]

Current-voltage characteristics have been measured for an ultrathin atomic-layer-deposited Al2O3 on GaAs as a function of film thickness, ambient temperature, and electric field. Current transport measurements indicate direct tunneling for 12–25 Å ultrathin films and typical Frenkel-Poole emission for 50–60 Å thick films. The maximum dielectric strength, which is of considerable importance for metal-oxide-semiconductor device applications, is studied thoroughly in this letter. The square root of the maximum dielectric strength is found to be roughly reversely proportional to the temperature from 500 to 300 K, and becomes constant below 200 K. The enhancement in the dielectric field strength observed from 300 to 200 K for the ultrathin insulating films can be adequately described using classical models. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) provides a unique opportunity to integrate high-quality gate dielectrics on III-V compound semiconductors. ALD Al2O3 is a high-quality gate dielectric on III-V compound semiconductor with low interface trap density, low gate leakage, and high thermal stability. The authors study the minority-carrier response of Al2O3/InGaAs metal-oxide-semiconductor (MOS) structures, which sheds light on the device physics for realizing high-performance inversion-type metal-oxide-semiconductor field-effect-transistor. The minority carriers in InGaAs do not respond to a small ac signal down to 100 Hz at 300 K, while they respond to up to 100 kHz at 500 K. Temperature dependent capacitance-voltage (C-V) measurement on the InGaAs MOS structure reveals the activation energy (Ea) of the minority-carrier recombination to be about 0.62 eV. [ABSTRACT FROM AUTHOR]

Atomic-layer deposition (ALD) provides a unique opportunity to integrate high-quality gate dielectrics on III-V compound semiconductors. We report detailed leakage current and breakdown electric-field characteristics of ultrathin Al2O3 dielectrics on GaAs grown by ALD. The leakage current in ultrathin Al2O3 on GaAs is comparable to or even lower than that of state-of-the-art SiO2 on Si, not counting the high-k dielectric properties for Al2O3. A Fowler-Nordheim tunneling analysis on the GaAs/Al2O3 barrier height is also presented. The breakdown electric field of Al2O3 is measured as high as 10 MV/cm as a bulk property. A significant enhancement on breakdown electric field up to 30 MV/cm is observed as the film thickness approaches to 1 nm. [ABSTRACT FROM AUTHOR]

This study examines terahertz radiation from a series of In0.52Al0.48As and GaAs surface-intrinsic-N+ structures (SIN+) with surface-intrinsic layers of various thicknesses. The built-in electric fields in the SIN+ structures are used as the bias. Experimental results indicate that the amplitudes of the THz emission are independent of the built-in electric fields in the emitters when the built-in electric fields exceed the corresponding critical electric fields of the semiconductors. In contrast, the amplitudes of the THz emission are proportional to the thickness of the intrinsic layer and, therefore, the number of photo-excited charged carriers. [ABSTRACT FROM AUTHOR]

Energy barriers at interfaces of (100)InP with atomic-layer deposited Al2O3 are determined using internal photoemission of electrons. The barrier height between the top of the InP valence band and bottom of the alumina conduction band is found to be 4.05±0.10 eV corresponding to a conduction band offset of 2.7 eV. An interlayer associated with the oxidation of InP may result in a lower barrier for electron injection potentially leading to charge instability of the insulating stack. A wide-gap P-rich interlayer has a potential to reduce this degrading effect as compared to In-rich oxides. [ABSTRACT FROM AUTHOR]