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An amorphous TaSiN metal gate (MG) is introduced into double-gate fin field-effect transistors (FinFETs) to suppress work function variation (WFV) of the MG, which is a dominant source of threshold voltage (Vt) variability for MG FinFETs. Comparing with a poly-crystalline TiN gate, the TaSiN gate reduces Vt variation dramatically and thus records the smallest AVt value of 1.34 mV μm reported so far for the MG-FinFETs. By decomposing the variation source due to interface trap density, the WFV suppression using the amorphous MG is confirmed to be effective to achieve the well-suppressed variability of the MG-FinFETs.

A fabrication technique for a vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with a standing-up ultrathin channel (UTC) and self-aligned source and drain (S/D) is proposed. A 20nm thick vertical UTC with low channel thickness fluctuation was formed on a (110)-oriented Si substrate using orientation-dependent wet etching. The top and bottom S/D were self-aligned to the DGs by using a combination of ion implantation and solid-phase diffusion. The fabricated vertical DG MOSFETs revealed that the channel thickness less influences the threshold voltage. Furthermore, a low sub-threshold slope of 68.8mV/decade was achieved with a channel thickness of 20nm.

Work function control of metal transistor gates was implemented with Al–Ni alloys. In addition to obtaining conventional capacitance-voltage (C-V) measurements to evaluate the work function, we microscopically characterized the work function distribution through scanning Maxwell-stress microscopy (SMM). The C-V curves of the Al–Ni alloys that we investigated exhibited work functions approximately between those of Al and Ni. The SMM analysis revealed that an Al–Ni alloy fabricated by the interdiffusion of a Ni∕Al stack had a significant nonuniformity of the work function. This nonuniformity correlated with degradation of the C-V characteristics for interdiffused Al–Ni alloys.