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We have fabricated lateral surface superlattices by etching a strained layer of In0.2Ga0.8As near the surface of a heterostructure. This provides strong modulation of the electron gas while retaining a high electron mobility. The potential arises mainly from strain and the piezoelectric effect, which depends on orientation, and from the change in the surface profile. The fundamental components of these two contributions cancel in one orientation to leave a dominant second harmonic. This effectively halves the period of the superlattice from its lithographic value and provides a promising technique for creating potentials with a period comparable to the Fermi wavelength.

We report on the experimental realization of a quantum point contact in a semiconductor heterostructure by lithography with an atomic force microscope (AFM). A thin, homogeneous titanium film on top of the chip surface was patterned by local anodic oxidation, induced by a current applied to an n-doped AFM tip. We demonstrate that self-aligned gate structures in the sub-micron regime can be fabricated with this technique.

We demonstrate single electron charging in fully controllable nanoscale quantum devices at temperatures above 4 K. Hitherto, single electron devices operating at ‘‘high’’ temperatures have been two‐terminal, having no control electrode, whereas fully tunable structures such as quantum dots have only shown charging effects at temperatures of 4 K or less. We have fabricated ultrasmall quantum dots on modulation doped heterostructures where the two‐dimensional electron gas is less than 30 nm from the surface. Dots with lithographic diameter 150 nm show Coulomb oscillations up to temperatures of 7 K. Higher temperature operation allows potential applications to be considered without the need, for example, of a dilution fridge.

Periodic arrays of 150 and 175 nm‐wide GaAs–AlAs quantum wires and quantum dots were investigated, fabricated by electron beam lithography, and SiCl4/O2 reactive ion etching, by means of reciprocal space mapping using triple axis x‐ray diffractometry. From the x‐ray data the lateral periodicity of wires and dots, and the etch depth are extracted. The reciprocal space maps reveal that after the fabrication process the lattice constant along the growth direction slightly increases for the wires and even more so for the dots.

We describe a novel technique using an atomic force microscope (AFM) for integrated nanometer‐scale lithography on various mask materials such as photoresist or gold covering a mesa‐etched GaAs‐AlGaAs heterostructure at ambient conditions. The generated patterns can be transferred to the two‐dimensional electron gas by wet chemical etching or by ion beam irradiation. We succeed in fabricating hole arrays with a periodicity down to 35 nm and a hole diameter of only a few nanometers. In magnetoresistance studies on so‐called antidot devices with 95 nm period at T=4.2 K we can clearly observe commensurability oscillations, demonstrating the successful pattern transfer to the electron system. With the AFM we can also pattern lines of varying width and depth into prefabricated devices.

We study the photocurrent of quantum capacitor devices consisting of an electron wire array induced in an undoped AlAs/GaAs heterojunction with an interdigitated gate electrode. The photocurrent measures the collective one‐dimensional intersubband resonance in the electron wires. The new technique to measure fundamental excitations of nanostructured electron systems yields strong signals even at very low electron densities so that only a single one‐dimensional subband is occupied. Compared to previous far‐infrared transmission studies the length and the number of the wires averaged in our technique is substantially smaller. The intersubband resonance in our devices is tunable in a wide range of energies up to 10.5 meV.

A model for the effects of dry‐etch damage on the conductances of etched structures is developed. Expressions for defect distribution are obtained for top‐surface and sidewall damage. The expression for sidewall damage is used in the calculation of wire conductances. The model accounts accurately for changes in experimentally measured conductances of SiCl4‐etched n+‐GaAs wires with variations in material carrier concentration, epilayer thickness, and etch time/depth. The analysis indicates that defects are created at a significant rate at sidewalls as compared to top surfaces.

The effect of varying the temperature (T cr) of an As4→As2 cracker furnace between 600 and 700 °C on the properties of GaAs grown by molecular beam epitaxy has been evaluated using 4–300 K Hall measurements and 4.2 K far‐infrared photoconduction spectroscopy, in an extension of earlier work on high‐mobility material (Ref. 1). The residual donors are silicon and sulphur with mid‐1013 cm−3 concentrations under As2‐growth conditions (T cr=700 °C). By lowering T cr, the silicon concentration is reduced substantially, leaving sulphur as the principal impurity. A 15‐μm‐thick layer grown with T cr=650 °C has measured free‐electron densities of ≊2.8×1013 cm−3 and peak mobilities ≊4×105 cm2 V−1 s−1 at ≊28–42 K, the highest ever recorded in bulk GaAs.

Exceptionally pure n‐GaAs has been grown without intentional doping by solid‐source molecular beam epitaxy (MBE) using arsenic dimers (As2). Peak electron mobilities in the range 2.75–3.32×105 cm2 V−1 s−1 at temperatures of ≊40–50 K with free‐electron densities n=1×1014 cm−3 have been measured for a series of layers grown under a variety of conditions. These mobilities are among the highest recorded for MBE‐grown GaAs.

We describe the electrical properties of atomic layer deposited TiO2/Al2O3 bilayer gate oxides which simultaneously achieve high gate capacitance density and low gate leakage current density. Crystallization of the initially amorphous TiO2 film contributes to a significant accumulation capacitance increase (∼33%) observed after a forming gas anneal at 400 °C. The bilayer dielectrics reduce gate leakage current density by approximately one order of magnitude at flatband compared to Al2O3 single layer of comparable capacitance equivalent thickness. The conduction band offset of TiO2 relative to InGaAs is 0.6 eV, contributing to the ability of the stacked dielectric to suppress gate leakage conduction.