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We report on DC and microwave electrical transport measurements in silicon-on-insulator nano-transistors at low and room temperature. At low source-drain voltage, the DC current and radio frequency response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature are accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature [ABSTRACT FROM AUTHOR]

The continuous downscaling of transistors results in nanoscale devices which require fewer and fewer charged carriers for their operation. The ultimate charge controlled device, the singleelectron transistor (SET), controls the transfer of individual electrons. It is also the most sensitive electrometer, and as a result the electron transport through it can be dramatically affected by nearby charges. Standard direct-current characterization techniques, however, are often unable to unambiguously detect and resolve the origin of the observed changes in SET behavior arising from changes in the charge state of a capacitively coupled trap. Using a radio-frequency (RF) reflectometry technique, we are able to unequivocally detect this process, in very close agreement with modeling of the trap's occupation probability. [ABSTRACT FROM AUTHOR]

We perform an excited state spectroscopy analysis of a silicon corner dot in a nanowire field-effect transistor to assess the electric field tunability of the valley splitting. First, we demonstrate a back-gate-controlled transition between a single quantum dot and a double quantum dot in parallel which allows tuning the device into corner dot formation. We find a linear dependence of the valley splitting on back-gate voltage, from 880 μeV to 610 μeV with a slope of −45 ± 3 μeV/V (or equivalently a slope of −48 ± 3 μeV/(MV/m) with respect to the effective field). The experimental results are backed up by tight-binding simulations that include the effect of surface roughness, remote charges in the gate stack, and discrete dopants in the channel. Our results demonstrate a way to electrically tune the valley splitting in silicon-on-insulator-based quantum dots, a requirement to achieve all-electrical manipulation of silicon spin qubits. [ABSTRACT FROM AUTHOR]

Pre-strained fin-patterned Si/SiGe multilayer structures for sub-7 nm stacked gate-all-around Si-technology transistors that have been grown onto bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator, and compressive SiGe-On-Insulator were investigated. From strain maps with a nanometer spatial resolution obtained by transmission electron microscopy, we developed 3D quantitative numerical models describing the mechanics of the structures. While elastic interactions describe every other system reported here, the patterning on the compressive SiGe-On-Insulator substrate that is fabricated by Ge-condensation results in relaxation along the semiconductor/insulator interface, revealing a latent plasticity mechanism. As a consequence, Si layers with a uniaxial stress of 1.4 GPa are obtained, bringing fresh perspectives for strain engineering in advanced devices. These findings could be extended to other semiconductor technologies. [ABSTRACT FROM AUTHOR]

We report on the hole compact double quantum dots fabricated using a conventional CMOS technology. We provide the evidence of Pauli spin blockade in the few hole regime that is relevant to spin qubit implementations. A current dip is observed around zero magnetic field, in agreement with the expected behavior for the case of strong spin-orbit. We deduce an intradot spin relaxation rate ≈120 kHz for the first holes, an important step towards a robust hole spin-orbit qubit. [ABSTRACT FROM AUTHOR]