Search

We report the architecture and the performances of a memory based on a single field-effect transistor built on paper able to write-erase and read. The device is composed of natural multilayer cellulose fibers that simultaneously act as structural support and gate dielectric; active and passive multicomponent amorphous oxides that work as the channel and gate electrode layers, respectively, complemented by the use of patterned metal layers as source/drain electrodes. The devices exhibit a large counterclockwise hysteresis associated with the memory effect, with a turn-on voltage shift between 1 and -14.5 V, on/off ratio and saturation mobilities of about 104 and 40 cm2 V-1 s-1, respectively, and estimated charge retention times above 14 000 h. [ABSTRACT FROM AUTHOR]

Developing high quality GaN/dielectric interfaces is a fundamental step for manufacturing GaN vertical power transistors. In this paper, we quantitatively investigate the effect of planar etching treatment and trench formation on the performance of GaN-based MOS (metal oxide semiconductor) stacks. The results demonstrate that (i) blanket etching the GaN surface does not degrade the robustness of the deposited dielectric layer; (ii) the addition of the trench etch, while improving reproducibility, results in a decrease in the breakdown performance compared to the planar structures. (iii) For trench structures, the voltage for a 10 year lifetime is still above 20 V, indicating a good robustness. (iv) To review the trapping performance across the metal-dielectric-GaN stack, forward-reverse capacitance–voltage measurements with and without stress and photo-assistance are performed. Overall, as-grown planar capacitors devoid of prior etching steps show the lowest trapping, while trench capacitors have higher interface trapping and bulk trapping comparable to the blanket etched capacitors. (v) The nanostructure of the GaN/dielectric interface was characterized by high resolution scanning transmission electron microscopy. An increased roughness of 2–3 monolayers at the GaN surface was observed after blanket etching, which was correlated with the higher density of interface traps. The results presented in this paper give fundamental insight on how the etch and trench processing affects the trapping and robustness of trench-gate GaN-metal-oxide-semiconductor field effect transistors and provide guidance for the optimization of device performance. [ABSTRACT FROM AUTHOR]

The solution processed method has been wildly used in the thin film fabrication because of the advantages of low cost, high efficiency, large scale for production, and long-term stability. In this paper, a normally-off hydrogen-terminated diamond field-effect transistor (FET) has been realized by using a solution processed SnO2 (sp-SnO2) film as an insulator layer. X-ray photoelectron spectroscopy results demonstrated the stoichiometry of the sp-SnO2 film, which shows good insulator properties with leakage current density less than 2.1 × 10−5 A·cm−2 at gate voltages from −6.0 to 6.0 V. The drain–source current maximum, threshold voltage, extrinsic transconductance maximum, and effective mobility of the FET with a gate length of 10 μm are −17.6 mA·mm−1, −0.5 V, 5.7 mS·mm−1, and 41.3 cm2/V s, respectively. According to the capacitance voltage characteristic, the enhancement mode could be ascribed to the high positive fixed charge density in the sp-SnO2 film, which will repel the hole in the channel. This paper provides a simple method and a low temperature process to fabricate an insulator layer. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate reconfigurable ferroelectric field-effect transistors (Fe-FETs) exhibiting process dependence based on poly(vinylidene fluoride-trifluoroethylene)/molybdenum telluride[P(VDF-TrFE)/MoTe2] heterostructures. By introducing a thickness gradient to a ferroelectric polymer, we constructed a gradient distribution of coercive voltage. This enables programmable configuration of the device (n–p, p–n, p–p, or n–n) depending on the input voltage sequence. Our Fe-FETs exhibit multilevel storage capacity and logic ability, including an on/off ratio of 106, an adjustable rectification ratio from 1 to 45, and a reversible rectification direction. The use of such a structure-gradient design in an Fe-FET provides a valuable strategy for realizing process-dependent reconfigurability and the creation of intelligent devices. [ABSTRACT FROM AUTHOR]

Gate-tunable Josephson junctions are interesting for quantum technology applications, such as gatemon qubits and topological Majorana-based qubits. Furthermore, high-frequency compatible geometries can be utilized for implementing electrically pumped parametric amplifiers. In this paper, we combine processing, measurements, and modeling of near-surface InGaAs Josephson field-effect transistors in order to facilitate circuit simulations of actual non-ideal devices. We developed a compact model using Verilog-A and confirmed the validity of our model by accurately reproducing our measured data by circuit simulations in Advanced Design System. From the circuit simulations, an effective gate-dependent transmission coefficient, with a peak value of ∼ 3.5%, was extracted, mainly limited by contact transparency. [ABSTRACT FROM AUTHOR]

In this paper, a quantitative analysis is performed focusing on the read-after-write latency (RWL) phenomenon in HfOX-based ferroelectric field-effect transistors with a metal-ferroelectric-insulator-semiconductor structure. RWL is scrutinized by modifying two variables: the pulse width (tp) for the "write 1" operation and the operating temperature (T); the response of the charge component is found to follow an emission mechanism. Additionally, we identified a notable change in charge behavior at a specific temperature (Tb), where capture and emission are in balance. Experimental investigations have demonstrated that the activation energy (EA) for these charge components is situated between 0.2 and 0.5 eV, and the Tb is ∼50 °C. By elucidating the relationship between T, tp, remnant polarization (Pr), and Tb, we offer insights into the importance of optimizing tp and Pr on the transient response of the balanced charge and the related RWL phenomenon. [ABSTRACT FROM AUTHOR]

Demand for the detection of poisonous arsenic ions in water is increasing due to uncontrolled industrial and human activities. Conventional detection methods are found to be very complex, cumbersome, and non-portable. This paper presents curcumin functionalized zinc oxide field effect transistor for selective detection of arsenic ions in water, with high sensitivity and stability. The operating voltage of the device is optimized to 2.9 V through output characteristics, which ensures low power consumption. The presence of curcumin on ZnO surface imparts high degree of selectivity toward arsenic ions, and ZnO nanorods ensures high surface to volume ratio for adsorption. The device is tested against eight metal ions commonly found in water and is found to be highly selective toward arsenic. The device exhibits a sensitivity of 102 nA/ppb at zero gate voltage, which is further amplified to 366 nA/ppb by applying 2.4 V gate bias. The application of gate bias plays a pivotal role for enhancing the device sensitivity by 266% for 5 ppb arsenic concentration. The sensor shows a response time of 67 s and is found to be highly stable against adverse conditions. The sensor shows high resilience in the degradation of sensing performance for a duration of 40 days. Therefore, curcumin functionalized zinc oxide field effect transistor with proper gate bias shows promising results to be used as a portable, low-cost, and user-friendly arsenic ion detector system in future. [ABSTRACT FROM AUTHOR]

Field-effect transistor (FET)-based biosensors have demonstrated highly sensitive label-free detection of a plethora of biomolecules as next-generation binding assays. While the dose–response curve of affinity-based binding assays generally has a nonlinear shape, any distortion contributed by the FET transducers has not been well understood. In this paper, we show that the signal transduction of FET sensors plays an important role in shaping their dose–response curves when operating in the nonlinear screening regime. We have found that the nonlinearity arising from the counterion screening in the electrical double layer could distort the relationship between the device flatband voltage shift and the analyte concentrations in (1) lowering its half-maximal response concentration as well as the sensitive detection range and (2) expanding its dynamic range. Negligence of such nonlinearity would introduce errors in the extracted affinity properties of the analyte–receptor pair. This work provides useful guidelines for designing FET-based binding assays and interpreting their measurement data. [ABSTRACT FROM AUTHOR]

A normally-off inversion p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a nitrogen (N)-doped diamond body deposited using microwave plasma-enhanced chemical vapor deposition (MPECVD) was fabricated. The MOSFET exhibited a drain current density of −1.7 mA/mm. Thus far, this value is similar to the device performance of the inversion p-channel MOSFET fabricated using a phosphorus (P)-doped n-type diamond body. The N2 used for N-doping is safer than the PH3 used for P-doping; moreover, the doping concentration is highly controllable. Because the MOSFET, which is a classical electronic device, is driven by a gate voltage, smooth functioning was possible even at a deep donor level. The observed characteristics of the classic MOSFET operating via an N-doped body are crucial for the development of diamond power devices. In this paper, we discuss the significance of the N-doped diamond body and electrical characteristics of the inversion p-channel MOSFET fabricated using an N-doped diamond body. [ABSTRACT FROM AUTHOR]

In this paper, negative transconductance (NTC) behavior in molybdenum disulfides (MoS2) field effect transistors (FETs) is investigated. Combining experimental observation and numerical analysis, we demonstrate that positive shift in the device transfer curves results from the electron trapping/de-trapping processes, where the defect densities at the MoS2/SiO2 interface are reduced when the temperature T decreases from 300 to 200 K. Moreover, the main types of defects that affect the device electrical performance are the interface defect and bulk sulfur vacancy VS in which VS induces the p-type doping effect. While decreasing T below 100 K, NTC occurs when their active layer thickness t (=41 and 35 nm) is larger than the Debye length λ (28 nm). Considering the n-type doping effect induced by the interface defects and the p-type doping caused by the bulk S vacancies, these two opposite doping regions are carefully implemented in simulation at T = 70 K. A vertical barrier induced by the inhomogeneous electron distribution enlarges with the increased gate bias VGS and, thereafter, leads to the unconventional increase in the contact and total resistances with t > λ. While t ≦ λ, the barrier and NTC behavior disappear. The current IDS and transconductance g obtained from the simulation confirm the low-temperature NTC mechanism related to the defects as discussed above. The material defects and physical origin of NTC discussed in the multilayer MoS2 transistors provide the theoretical foundation for designing and realizing novel structures of functional devices via defect engineering in the two-dimensional FET. [ABSTRACT FROM AUTHOR]

Negative capacitance (NC) field-effect transistors have great potential as next-generation low-power transistors due to their ability to overcome the Boltzmann limit. However, the fundamental physical mechanism of negative capacitance (NC) has not yet been clarified. This paper investigates the thermodynamic driving force of transient NC in the series circuit of a resistor and ferroelectric capacitor (R–FEC). We find that the widely applied Landau–Khalatnikov theory, which describes the minimization of Gibbs free energy, has the limitation to understand transient NC. The thermodynamic driving force of the transient NC is the minimization of the difference between the elastic Gibbs free energy and electric polarization work. Moreover, we find that the appearance of transient NC phenomenon is not due to the widely accepted viewpoint that the ferroelectric polarization goes through the negative curvature region of elastic Gibbs free energy landscape (Ga). Instead, after the energy barrier of Ga disappears, the transient NC phenomenon appears when the electric field across the ferroelectric material reaches local maximum. Furthermore, our results show that this process depends on both the intrinsic parameters of the ferroelectric material and the extrinsic factors in the R–FEC circuit. [ABSTRACT FROM AUTHOR]

Piezoelectricity of two-dimensional layered materials is of great significance for electromechanical coupling applications in nanoelectromechanical systems. The nanoscale devices based on graphene have attracted intense interest due to its excellent electronic and mechanical properties. However, the centrosymmetric crystal structure in intrinsic graphene severely restricts its applications in mechanical sensors, transducers, and energy harvesters. In this paper, a self-powered vibration sensing element based on rolled-up single-layer graphene is proposed and demonstrated, which realizes the conversion from mechanical vibrations into electrical signals. In contrast to previous pioneering works requiring silica cavities or Si/SiO2 calibration grating substrate to support the graphene, a three-dimensional (3D) non-closed tubular structure is adopted to develop the piezoelectricity in single-layer graphene, where the inversion symmetry of single-layer graphene is broken via self-rolled-up process induced strain. Hence, apparent piezoresponse from the 3D non-closed tubular graphene field effect transistor is observed. Moreover, a peak-to-peak amplitude for the piezoelectric current up to 4.2 is achieved, corresponding to the periodicity of mechanical vibration, and the value can increase to 10.8 nA by applying a small source–drain voltage of 6 mV. The device is also sensitive to mechanical vibration with different frequencies and shows similar currents. The electromechanical coupling in rolled-up graphene provides a basis for the applications in sensing, actuating, and energy harvesting. [ABSTRACT FROM AUTHOR]

This paper studies a composite device composed of ferroelectric random access memory (FeRAM) and metal-oxide-semiconductor field effect transistor. The relationship between the hysteresis characteristics and VG is reported, and the on/off ratios under different writing voltages are presented. The gm–VG curve of the forward and reverse sweeping shows that under forward sweep a very clear instability appears while voltage increases. The reasons for this can be explained according to the voltage divider rule, the ID formula, and gm formula of transistors, which show that there is polarization of the ferroelectric material. Accordingly, a method is proposed to determine the critical point of the ferroelectric capacitor polarization in this 1T1C structure, which is advantageous because it identifies the appropriate reading voltage necessary for an effective program state of the 1T1C device. This method was shown in three 1T1C and three FeRAMs devices with different ferroelectric areas. Finally, this method was verified by the P–V loop of FeRAMs. [ABSTRACT FROM AUTHOR]

Although the surface conductivity of a hydrogen-terminated diamond (H-diamond) enables production of high-performance field effect transistors (FETs), the total ionizing dose effect is yet to be clarified for H-diamond FETs. We fabricated a RADiation hardened H-terminated Diamond metal–oxide–semiconductor FET (RADDFET) using an oxide gate dielectric deposited at high temperatures. This paper describes its stable operation after 1 MGy irradiation. H-diamond films were prepared using microwave plasma assisted chemical vapor deposition with a p+ layer for reduction of contact resistance. The Al2O3 passivation layer was deposited by atomic layer deposition at 450 °C to achieve operation in high-temperature environment; then a RADDFET was fabricated on them using a Ru electrode. Several current–voltage characteristics were compared before irradiation and after certain dose levels up to 1 MGy. Before they were irradiated in air, the dose rate was measured using a cellulose triacetate film dosimeter. Even after an irradiation level of 1 MGy, the off-current at gate bias voltage (VG) of 3 V was more than six orders of magnitude lower than the on-current at VG of −6 V. Variation of the drain current density (JDS) in the measurements was less than 2%. The threshold voltage shifted approximately 1.7 V with 3 kGy of x ray irradiation, but no marked degradation was confirmed at higher levels. The subthreshold swings were 238, 215, and 264 mV/decade, respectively, after irradiation of 100 kGy, 300 kGy, and 1 MGy. These results indicate that the RADDFET was very stable at higher doses after initial stabilization. [ABSTRACT FROM AUTHOR]

The research community has invested heavily in semiconducting two-dimensional (2D) materials, such as transition metal dichalcogenides (TMDs). Their stability when scaled down to a few atoms thick makes them attractive candidates to replace or supplement silicon in many future technologies. Although this sentiment is prevalent, demonstrations of 2D field-effect transistors (FETs) often do not present their data in a way that enables a straightforward comparison. For example, some papers solely use mobility as the figure of merit, while others focus on unnormalized device on-current. Here, we benchmark the performance of a selection of 2D FETs with field-corrected metrics that allow a more accurate projection of their potential; while the demonstrated methods are by no means comprehensive, they provide insight into improved benchmarking of 2D FETs going forward. Importantly, we show that appropriate benchmarking requires consideration of the specific application, with the three dominant potential application areas of front-end-of-line (FEOL) high-performance FETs, back-end-of-line (BEOL) 3D-integrated FETs, and low-cost thin-film FETs (or TFTs) each demonstrated. We find that 2D materials have the potential to compete with silicon as the channel in scaled FEOL high-performance devices. Meanwhile, in BEOL applications, FETs from in situ synthesized 2D materials have performance limited by their low crystal quality – a result of the stringent thermal budget of BEOL fabrication, which necessitates the use of transferred 2D materials. In the TFT area, 2D materials are simpler to fabricate than their silicon-based counterparts and they are competitive with other material alternatives. As promising as these findings are, there remain many hurdles for 2D materials to overcome, including poor reliability, performance variability, and fabrication scalability. Continuous research effort, combined with appropriate benchmarking, is strongly encouraged. [ABSTRACT FROM AUTHOR]

This paper reports a self-induced ferroelectric 2-nm-thick Ge-doped HfO2 (Ge:HfO2) thin film. Ge thermal desorption, incorporation into HfO2, and further Ge:HfO2 crystallization were all performed through rapid thermal annealing simultaneously. The ferroelectric property of a 2-nm-thick Ge:HfO2/2-nm-thick Al2O3 dielectric stack was confirmed using the polarization-electric field measurement. X-ray photoelectron spectroscopy was used to confirm that Ge bonded to HfO2 as Hf-germanates. Piezoresponse force microscopy was used to demonstrate the piezoelectric property of Ge:HfO2/Al2O3. Furthermore, a dielectric stack of Ge:HfO2/Al2O3 was applied as a gate insulator in a Ge nanowire gate-all-around ferroelectric field-effect transistor (Ge NW Fe-GAAFET). The device exhibited a minimum steep-sub-threshold slope of 47 mV/dec, a high ION/IOFF ratio of >106, and low gate leakage current; moreover, it was free of a drain-induced barrier lowering effect. The proposed self-induced ferroelectric Ge:HfO2 Ge NW Fe-GAAFET is feasible for future ultra-low power integrated circuit applications. [ABSTRACT FROM AUTHOR]

The fermi-level pinning effect caused by low-order contact interface influences the performance of carbon nanotube (CNT) network field-effect transistors (FETs). In this paper, ambipolar CNT network FETs subjected to van der Waals (vdW) contact are demonstrated with the negligible Fermi-level pinning effect by using a physical transfer approach. The vdW contact method allows for the metal and CNT network to retain their intrinsic states without direct chemical bonding and interface interactions, leading to low injection barrier and contact resistance (Rc). Therefore, the field-effect mobilities of vdW metal-semiconductor (MS) contact devices in regions of dominance of the holes (μp) and electrons (μn) were 18.71 and 2.4 cm2 V−1 s−1 and yielded enhancements 2 and 10 times, respectively, beyond those of devices with typically evaporated electrodes. In addition, to develop ambipolar devices with balanced output capability, two-dimensional materials (h-BN and graphene) were inserted into the MS interface to tune the injection barrier. Because the metal work function was effectively reduced by inserting the h-BN layer, devices with h-BN inserted obtained values of μp and μn of 15.85 and 5.1 cm2 V−1 s−1, respectively. For devices with graphene, because of its field-modulated band alignment capability, μn improved to 8.38 cm2 V−1 s−1, while μp dropped slightly to 17.5 cm2 V−1 s−1. Therefore, the vdW contact method is a highly efficient integration strategy for high-performance CNT network FETs, and the different insertion layers can efficiently tune the ambipolar transportation of CNT network FETs rather than using different contact metals. This research provides an avenue for the design of future CNT network-based electronics. [ABSTRACT FROM AUTHOR]

A β-Ga2O3 field effect transistor (FET) outperforms a GaN FET in Baliga's figure of merit (FOM) by 400% and Huang's chip area manufacturing figure of merit by 330%, suggesting that β-Ga2O3 could be a substrate of choice for next generation power transistors. However, its low thermal conductivity leads to extreme self-heating, which deteriorates the device performance during high voltage operation. A holistic evaluation of performance from a material-device-circuit perspective is necessary before reaching any conclusion regarding the technological viability of β-Ga2O3. In this paper, we develop a multiphysics and multiscale model for a material-device-circuit analysis of β-Ga2O3 FETs. The framework allows us to explore the effectiveness of various device design strategies (e.g., thermal shunts) for mitigating the thermal chokepoints and compare the performance of improved β-Ga2O3 FETs against that of GaN and SiC FETs. We highlight the limitations of traditional FOMs to analyze the relative performance of the new generation of power transistors whose structure incorporates stacked layers of materials with different thermal conductivities, like those of β-Ga2O3 FETs. We suggest device design strategies, such as wafer thinning, incorporation of heat shunts, and improved channel mobility, so that β-Ga2O3 FETs can compete commercially with GaN and SiC technologies. [ABSTRACT FROM AUTHOR]

In 4H silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs), slow drain current transients and strong sweep hysteresis govern the subthreshold regime, in particular, after negative gate stress. Although these are clearly charge carrier trapping and emission phenomena, a physical model describing the effect to a full extent is missing. In this paper, we investigate a-face n-channel 4H-SiC trench MOSFETs and record drain current transients over seven decades of time for gate voltages below and above threshold. We find clear evidence that the transients result from electron capture rather than from hole emission. Thereby, the time constant for electron capture into interface or near-interfacial defects is broadly distributed and is well characterized by a lognormal distribution. Based on the findings, we propose a physical model that consistently describes the time-dependent measured data in the full gate voltage range. The resulting trap density for the investigated MOSFETs equals 4.2 × 1012 cm–2 with a median electrical capture cross section of 2.5 × 10 − 19 cm2. The distribution of capture time constants has a width of 1.6 orders of magnitude. [ABSTRACT FROM AUTHOR]

The temperature dependence of the tunneling transport characteristics of Si diodes with an isoelectronic impurity has been investigated in order to clarify the mechanism of the ON-current enhancement in Si-based tunnel field-effect transistors (TFETs) utilizing an isoelectronic trap (IET). The Al-N complex impurity was utilized for IET formation. We observed three types of tunneling current components in the diodes: indirect band-to-band tunneling (BTBT), trap-assisted tunneling (TAT), and thermally inactive tunneling. The indirect BTBT and TAT current components can be distinguished with the plot described in this paper. The thermally inactive tunneling current probably originated from tunneling consisting of two paths: tunneling between the valence band and the IET trap and tunneling between the IET trap and the conduction band. The probability of thermally inactive tunneling with the Al-N IET state is higher than the others. Utilization of the thermally inactive tunneling current has a significant effect in enhancing the driving current of Si-based TFETs. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a volatile atomic switch that can be utilized for obtaining steep subthreshold swing (SS) (<5 mV/dec) characteristics in FETs. We propose a CMOS-compatible atomic switch (W/Cu2S/W) that demonstrates volatility and immunity to the voltage–time dilemma. Furthermore, we enhance the device characteristics by examining the composition control, scaling of device size, and film thickness. Then, the atomic switch is integrated with a conventional transistor that has a large SS (>60 mV/dec). The result shows an improvement in the SS, which results from the transition of the atomic switch between the ON and OFF states, which is caused by the formation and rupture of a conductive filament. As a result, excellent switching characteristics are obtained for the FETs, such as low IOFF (∼10−5μA/μm), high ION/IOFF ratio (∼105), low VDD (∼0.25 V), and steep SS (<5 mV/dec). [ABSTRACT FROM AUTHOR]

This paper presents graphene field-effect transistor (GFET) based pressure sensors for tactile sensing. The sensing device comprises GFET connected with a piezoelectric metal-insulator-metal (MIM) capacitor in an extended gate configuration. The application of pressure on MIM generates a piezo-potential which modulates the channel current of GFET. The fabricated pressure sensor was tested over a range of 23.54–94.18 kPa, and it exhibits a sensitivity of 4.55 × 10−3 kPa−1. Further, the low voltage (∼100 mV) operation of the presented pressure sensors makes them ideal for wearable electronic applications. [ABSTRACT FROM AUTHOR]

The growth of III-V semiconductors on Si generates defects at the III-V/Si interface which are known to degrade the performance of electronic devices where this interface is an active region. This paper presents a density functional theory based analysis of the InAs/Si interface with the aim to find the origin of traps at this interface. The optimized structure is obtained by structural minimization and is compared with a filtered Transmission Electron Microscopy image from the literature. The good qualitative agreement between the two results validates the atomic model of the InAs/Si interface. Electronic structural calculations are performed on the geometrically optimized InAs/Si slab to identify the interface trap levels. The study reveals that the InAs/Si interface traps originate from unsaturated orbitals present on Arsenic interface atoms. The saturation of the unsaturated As atoms by H or S is able to passivate the interface and to reduce the Dit. [ABSTRACT FROM AUTHOR]

To extend the frequency range of transistors into the terahertz domain, new transistor technologies, materials, and device concepts must be continuously developed. The quality of the interface between the involved materials is a highly critical factor. The presence of impurities can degrade device performance and reliability. In this paper, we present a method that allows the study of the charge carrier velocity in a field-effect transistor vs impurity levels. The charge carrier velocity is found using high-frequency scattering parameter measurements followed by delay time analysis. The limiting factors of the saturation velocity and the effect of impurities are then analysed by applying analytical models of the field-dependent and phonon-limited carrier velocity. As an example, this method is applied to a top-gated graphene field-effect transistor (GFET). We find that the extracted saturation velocity is ca. 1:4 × 107 cm/s and is mainly limited by silicon oxide substrate phonons. Within the considered range of residual charge carrier concentrations, charged impurities do not limit the saturation velocity directly by the phonon mechanism. Instead, the impurities act as traps that emit charge carriers at high fields, preventing the current from saturation and thus limiting power gain of the GFETs. The method described in this work helps to better understand the influence of impurities and clarifies methods of further transistor development. High quality interfaces are required to achieve current saturation via velocity saturation in GFETs. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate why cubic Rashba spin splitting is observed within inverted doped strained germanium (sGe) hetrostructures. Magnetotransport measurements showed beating within the SdH oscillation, with fast Fourier analysis revealing cubic Rashba spin splitting to be present. A cubic Rashba coefficient of β=7.97×10-29 eVm3β=7.97×10-29 eVm3 and a spin-splitting energy of Δ=1.17 meVΔ=1.17 meV were determined. The source of the cubic Rashba spin splitting was identified from a combination of ultra low energy secondary ion mass spectrometry analysis and subsequent band structure modelling using Nextnano3. Ultra-low energy secondary ion mass spectrometry revealed an unintentional, highly B doped near surface region accounted for structure inversion asymmetry, whereas subsequent band structure modelling using Nextnano3 demonstrates how this asymmetric B doping generates structural inversion asymmetry within the sGe QW structure and cubic Rashba spin splitting realized. [ABSTRACT FROM AUTHOR]

Molybdenum disulfide (MoS2), a relatively new and exciting two-dimensional graphene-like material, has been attracting more and more attentions from the researchers due to its unique structural and fascinating properties. The potential application of MoS2 under high-pressure and low-temperature is expected, while the related research is few at present. In this paper, quadrilayer MoS2 was synthesized by chemical vapor deposition, and its structural properties under different pressures (0-20.7GPa) and temperatures (10-300K) were investigated via the Raman spectra. We find that the lattice of quadrilayer MoS2 is not damaged and the quadrilayer MoS2 exhibits good semiconductive properties under large variable pressures from atmospheric to 20.7GPa, which is much different to its bulk and single crystalline phases. In addition, the lattice structures of the quadrilayer MoS2 are stable in 10-300K, and the Grüneisen parameters of E12g and A1g modes are smaller than that of bulk. This study indicates that quadrilayer MoS2 has a better prospect in high-pressure and low-temperature environment. [ABSTRACT FROM AUTHOR]

Corrections to the article "Charge trapping at the MoSs-SiOs interface and its effects on the characteristics of MoSs metal-oxide-semiconductor field effect transistors" that was published online on may 19, 2016 are presented.

Metal-oxide-semiconductor (MOS) device is the basic building block for field effect transistors (FET). The majority of thin-film transistors (TFTs) are FETs. When MOSFET are mechanically bent, the MOS structure will be inevitably subject to mechanical strain. In this paper, flexible MOS devices using single crystalline Silicon (Si) and Germanium (Ge) nanomembranes (NM) with SiO2, SiO, and Al2O3 dielectric layers are fabricated on a plastic substrate. The relationships between semiconductor nanomembranes and various oxide materials are carefully investigated under tensile/compressive strain. The flatband voltage, threshold voltage, and effective charge density in various MOS combinations revealed that Si NM-SiO2 configuration shows the best interface charge behavior, while Ge NM-Al2O3 shows the worst. This investigation of flexible MOS devices can help us understand the impact of charges in the active region of the flexible TFTs and capacitance changes under the tensile/compressive strains on the change in electrical characteristics in flexible NM based TFTs. [ABSTRACT FROM AUTHOR]

Molybdenum disulfide is a promising channel material for field effect transistors (FETs). In this paper, monolayer MoS2 grown by chemical vapor deposition (CVD) was used to fabricate top-gate FETs through standard optical lithography. During the fabrication process, charged impurities and interface states are introduced, and the photoresist is not removed cleanly, which both limit the carrier mobility and the source-drain current. We apply a SiO2 protective layer, which is deposited on the surface of MoS2, in order to avoid the MoS2 directly contacting with the photoresist and the ambient environment. Therefore, the contact property between the MoS2 and the electrodes is improved, and the Coulomb scattering caused by the charged impurities and the interface states is reduced. Comparing MoS2 FETs with and without a SiO2 protective layer, the SiO2 protective layer is found to enhance the characteristics of the MoS2 FETs, including transfer and output characteristics. A high mobility of ~42.3 cm2/V s is achieved, which is very large among the top-gate CVD-grown monolayer MoS2 FETs. [ABSTRACT FROM AUTHOR]

This paper investigates the low-frequency noise properties of multilayer WSe2 field effect transistors (FETs) in subthreshold, linear, and saturation regime. The measured noise power spectral density of drain current (SID) shows that the low-frequency noise in multilayer WSe2 FET fits well to a 1/fγ power law with γ ~ 1 in the frequency range of 10Hz-200Hz. From the dependence of SID on the drain current, carrier mobility fluctuation is considered as a dominant low frequency noise mechanism from all operation regimes in multilayer WSe2 FET. Extracted Hooge's parameter in this study is within the value of 0.12, comparable to those of the transition metal dichalcogenide FETs in recent reports. [ABSTRACT FROM AUTHOR]

The term ambipolar has been used extensively in association with carbon nanotube and graphene-based field effect transistors, often in a varied manner, leading to a confused understanding of the term. Through the use of established scientific definitions and theoretical work on device operation, this paper attempts to clarify the understanding of the term and present a discussion of its appropriate use. [ABSTRACT FROM AUTHOR]

In this paper a lumped parameter electrical model for porous silicon junction field effect transistor (PSJFET) gas sensors is presented and experimentally validated. The PSJFET is an integrated p-channel JFET device modified with a porous silicon layer, the latter acting as sensing element. The model is described by using an analytical closed-form expression, which quantitatively links the sensor current to the analyte concentration in the environment, and validated by using experimental data of PSJFETs exposed to both synthetic air and NO2 with concentration of 300 ppb. Best fitting of experimental data with the proposed model allows one to get quantitative information on the effect of NO2 adsorption/desorption at the PS surface on electrical PS parameters, such as its conductance and surface charge density. [ABSTRACT FROM AUTHOR]

In this paper, we investigate on the capacitance behavior of radio-frequency interdigital capacitor with single- and multi-layer graphenes, 5-μm wide and 20-μm long, grown by chemical vapor deposition. From the obtained results, the self-resonance frequency of the capacitor alone is unaffected by adding single- and multi-layer graphenes. However, the capacitor with single-layer graphenes shows a lower capacitance peak compared to the two other configurations due to an increase of overall resistance by the single-layer graphene. As a result, we find that the performance of the overall capacitor can be dependent on the resistance of graphenes. [ABSTRACT FROM AUTHOR]

This paper presents materials, device designs, and physical/electrical characteristics of a form of nanotube electronics that is physically transient, in the sense that all constituent elements dissolve and/or disperse upon immersion into water. Studies of contact effects illustrate the ability to use water soluble metals such as magnesium for source/drain contacts in nanotube based field effect transistors. High mobilities and on/off ratios in transistors that use molybdenum, silicon nitride, and silicon oxide enable full swing characteristics for inverters at low voltages (~5V) and with high gains (~30). Dissolution/disintegration tests of such systems on water soluble sheets of polyvinyl alcohol demonstrate physical transience within 30 min. [ABSTRACT FROM AUTHOR]

N-type doping of graphene with long-term chemical stability in air represents a significant challenge for practical application of graphene electronics. This paper reports a reversible doping method to achieve highly stable n-type graphene nanomeshes, in which the SU-8 photoresist simultaneously serves as an effective electron dopant and an excellent encapsulating layer. The chemically stable n-type characteristics of the SU-8 doped graphene were evaluated in air using their Raman spectra, electrical transport properties, and electronic band structures. The SU-8 doping does minimum damage to the hexagonal carbon lattice of graphene and is completely reversible by removing the uncrosslinked SU-8 resist. [ABSTRACT FROM AUTHOR]

A channel suspension method to fabricate high performance graphene field effect transistors (GFET) is presented in this paper. The balance is reached between gate efficiency and carrier mobility. A GFET with 15 μm × 15 μm gate dimension achieves a high normalized transconductance. Peak intrinsic carrier mobility is extracted to be 44 600 cm2v-1s-1. Suspension of the graphene channel is confirmed by AFM, SEM, and gate capacitance measurements. Unlike traditional substrate supported GFET, the proposed suspended-channel structure suppresses the influence of extrinsic scatterings and, meanwhile, maintains a certain gate controllability. [ABSTRACT FROM AUTHOR]

Electric double layer transistors (EDLTs) have unique impedance properties. As the transport of charge in the semiconductor and of ions in the electrolyte involve different time scales, the gate-to-channel equivalent capacitance changes dramatically with frequency. An important feature is the coupling between the capacitance and the channel conductance in the frequency range of interest due to the relatively large time constant of the charging process. This paper presents a systematic study of these EDLT properties. An equivalent-circuit model is proposed that provides reasonable physical explanations and shows good agreement with the experimental results. [ABSTRACT FROM AUTHOR]

A main factor contributing to bias stress instability in organic transistors is charge trapping of mobile carriers near the gate insulator-semiconductor interface into localized electronic states. In this paper, we study the bias stress behavior in low-voltage (p-type) polyelectrolyte-gated organic field effect transistors (EGOFETs) at various temperatures. Stressing and recovery in these EGOFETs are found to occur six orders of magntiude faster than typical bias stress/recovery reported for dielectric-gated OFETs. The mechanism proposed for EGOFETs involves an electron transfer reaction between water and the charged semiconductor channel that promotes the creation of extra protons diffusing into the polyelectrolyte. [ABSTRACT FROM AUTHOR]

In this paper, we examine the dependence of channel length on the sensitivity of Schottky contacted silicon nanowire field-effect transistor sensors. The fabricated experimental devices are used as photosensors as well as chemical sensors for pH sensing. The difference in light illuminated current response depends on the channel length in the linear regime. However, the current ratio (ΔILight-Dark/IDark) shows a different trend, being much improved for a longer channel in the subthreshold regime, which can be explained by the different subthreshold swings. Finally, devices of two different channel lengths are applied to detect the pH value of a solution yielding results similar to photosensing. From these results, we suggest that it is desirable to shorten the channel if the sensor is working in the linear region and increase the channel length if the sensor is used in the subthreshold region. [ABSTRACT FROM AUTHOR]

This paper describes the plasmon resonances in AlN/GaN high electron mobility transistors. It is shown that wide tunable resonances with the frequency located at terahertz band can be obtained in this material system. The results originate from the ultra-high electron density induced by the polarization effect and higher order plasmon excitation. At room temperature, the dielectric response caused by phonon-polariton interactions obliterates the higher order plasmon resonances at frequency higher than 10 THz. However, the viscosity contribution to the damping of plasmons is very small in these devices. Our results also show the potential of this device for terahertz applications. [ABSTRACT FROM AUTHOR]

Hydrogen-terminated diamond surfaces, emerging as a promising two-dimensional (2D) electron platform with great thermal and electronic properties, hold great potential for the next-generation high power and high frequency field effect transistor (FET). However, ideal gate dielectrics with high crystallinity and defect-free surfaces are still largely elusive. In this work, using the contamination-free pickup transfer method, hexagonal boron nitride (h-BN) flakes were fabricated on top of the hydrogen-terminated diamond surface to serve as a gate material and the passivation layer. The morphological and optical characterizations revealed the formation of homogeneous and intimate interface between h-BN and diamond. Benefiting from the h-BN gate dielectric layer, the maximum drain current density, subthreshold swing, and on/off ratio of diamond FET are measured to be −210.3 mA mm−1, 161 mV/dec, and 106, respectively. Especially, the transport measurement shows an almost constant Hall mobility of around 260 cm2 V−1 s−1 in the hole density range of 2 − 6 × 1012 cm−2, suggesting the excellent gate controllability of h-BN. Our results indicate that h-BN could form high-quality interface with hydrogen-terminated diamond, paving the way for the development of diamond-based electronic applications. [ABSTRACT FROM AUTHOR]

We grow strained Ge/SiGe heterostructures by reduced-pressure chemical vapor deposition on 100 mm Ge wafers. The use of Ge wafers as substrates for epitaxy enables high-quality Ge-rich SiGe strain-relaxed buffers with a threading dislocation density of (6 ± 1) × 10 5 cm − 2 , nearly an order of magnitude improvement compared to control strain-relaxed buffers on Si wafers. The associated reduction in short-range scattering allows for a drastic improvement of the disorder properties of the two-dimensional hole gas, measured in several Ge/SiGe heterostructure field-effect transistors. We measure an average low percolation density of (1.22 ± 0.03) × 10 10 cm − 2 and an average maximum mobility of (3.4 ± 0.1) × 10 6 cm 2 / Vs and quantum mobility of (8.4 ± 0.5) × 10 4 cm 2 / Vs when the hole density in the quantum well is saturated to (1.65 ± 0.02) × 10 11 cm − 2 . We anticipate immediate application of these heterostructures for next-generation, higher-performance Ge spin-qubits, and their integration into larger quantum processors. [ABSTRACT FROM AUTHOR]

Lead zirconate titanate (PZT) is the promising candidate in advanced ferroelectric memory application due to its excellent piezoelectricity, ferroelectricity, pyroelectricity, non-linear dielectric behavior, multiferroic properties, high ferroelectric Curie temperature, and extremely strong stability. It has gained attention in the field beyond von-Neumann computing, which inspires the development of computation in memory applications. Various structures of the ferroelectric memristive device, including ferroelectric field effect transistor, tunnel junctions, nonvolatile memory, and capacitor, based on PZT have been proposed for the realization of computation in memory application. On the other hand, unique designs realize the performance enhancement of PZT ferroelectric memristive devices, i.e., the insertion of 2D material MXene. This perspective further points out some of the challenges that MXene-PZT based ferroelectric memristive devices encounter in reality and finally give our viewpoint on possible developments toward computation in memory in a neuromorphic platform. [ABSTRACT FROM AUTHOR]

Low-resistance contact has long been pursued in the two-dimensional (2D) electronic/optoelectronic device community. Still, an economy-efficient method highly compatible with the conventional 2D device fabrication process in laboratory remains to be explored. Herein, we report a plasma-optimized contact strategy for high-performance PdSe2 nanoflake-based field-effect transistors (FETs). Selenium vacancies created by air plasma can introduce p-type doping in the contact area, thus optimizing the device performance. The effect of plasma treatment on PdSe2 nanoflake is corroborated by high-resolution transmission electron microscopy, energy-dispersive x-ray spectroscopy spectrum, atomic force microscopy, and Kelvin probe force microscopy. The PdSe2 FET with plasma-optimized contact exhibits significantly improved field-effect carrier mobilities, current on/off ratios, and reduced contact resistance than that without plasma treatment fabricated from the same PdSe2 nanoflake. Moreover, this strategy has also been proven effective to prepare high-performance FETs based on 2D WSe2 and MoSe2 nanoflakes, further demonstrating its application prospect. [ABSTRACT FROM AUTHOR]

In this work, we investigate the reliability and stability of short-channel indium tin oxide (ITO) field-effect transistors through 1/f noise characterization at elevated temperature with positive bias temperature instability (PBTI). The 1/f noise behavior of a short-channel 60-nm-long channel ITO transistor can be described by the carrier number fluctuation model, suggesting that carrier trapping and de-trapping by trap states within the 5 nm thin high-κ HfLaO dielectric are the dominant mechanisms affecting 1/f noise. Small positive threshold voltage shifts of 0.042 and 0.057 V after PBTI measurements of 3000 s at 25 and 85 °C have been obtained, respectively. The higher gate leakage current at elevated temperature leads to an earlier breakdown in the time-dependent dielectric breakdown measurement. Furthermore, 1/f noise after PBTI has also been carried out at elevated temperature, and the degradations after stress can also be attributed to the stress induced traps inside the gate dielectric. [ABSTRACT FROM AUTHOR]

In this work, Al2O3-passivated, monolithic, and crystalline Al–Ge–Al heterostructure nanowire field effect transistors (FETs) with Ge channel lengths ranging from 18 to 826 nm are analyzed from a low-frequency noise perspective. 1/f and random telegraph noise (RTN) are analyzed in an accumulation mode, where the hole channel is formed by applying a back-gate potential VG. The normalized power spectral density of drain current fluctuations of 1/f noise (S I D / I D 2) at medium currents follows nearly an 1/ID trend. 1/f noise is analyzed within both the mobility and carrier number fluctuation models (MFM and CNFM), respectively. Taking the MFM into account, the Hooge noise parameter α spreads in the interval of 1.5 × 10−4 to 4 × 10−2, with lower values for shorter devices. Using the same data and the CNFM, the density of interface states Dit in the Al2O3/GexOy/Ge system was estimated using the transconductance extracted from the quasi-static transfer I/V characteristics. The extracted Dit values range from 5 × 109 to 3 × 1012 cm−2 eV−1. Contact noise has also been observed in some devices at high currents. RTN analyzed in time domain exhibits a relative RTN amplitude in the 0.3%–20% range. Capture and emission time constants as a function of VG exhibit a typical behavior for metal oxide semiconductor FETs. The extracted noise parameters are comparable with Ge and III–V nanodevices of top-down and bottom-up technologies. [ABSTRACT FROM AUTHOR]

We demonstrate n-type ferroelectric field-effect transistors (FeFETs) employing atomic-layer-deposited HfZrOx (HZO) films with a large memory window (MW) immediately after the write operation. Charge trapping at the HZO/Si interface in FeFETs is the primary source of memory window reduction. To control the properties of the interfacial layer, we varied the O3 injection time during atomic layer deposition. The HZO (long O3 of 7 s)-based FeFET demonstrated a large MW (2.1 V) in the DC transfer curves compared with the HZO (short O3 of 0.3 s)-based FeFET (0.9 V), although the bulk properties of the HZO films barely changed with the O3 injection time. In pulsed I–V measurements with an extremely short delay time of 100 ns between pulses, the HZO (long O3 of 7 s)-based FeFET showed a large MW of 1.0 V. Such improvements in the performance of HZO-based FeFETs indicate that the trap density in the interfacial layer is reduced by the use of a long O3 injection time. This is supported by the variation in the silicate/SiO2 ratio within the interfacial layer of the HZO films deposited at various O3 injection times. [ABSTRACT FROM AUTHOR]

Nanometer-scale transistors often exhibit random telegraph noise (RTN) with high device-to-device variability. Recent experiments up to Grad total ionizing dose (TID) demonstrate stable RTN in planar bulk-Si metal-oxide-semiconductor (MOS) transistors and in Si fin field-effect transistors (FinFETs). In these cases, pre-existing defects in the ultrathin gate dielectrics dominate the device low-frequency 1/f noise (LFN). In contrast, III–V MOS devices with lower quality oxide/semiconductor interfaces show significant increases in LFN at much lower doses, due to the TID-induced activation of high densities of border traps. Aggressively scaled devices fabricated in Si gate-all-around nano-wire FET technology exhibit prominent defects leading to LFN and RTN. Increases or decreases of LFN in these devices during irradiation and annealing results primarily from the activation or passivation of border traps and interface traps. [ABSTRACT FROM AUTHOR]

To support the ever-growing demand for faster, energy-efficient computation, more aggressive scaling of the transistor is required. Two-dimensional (2D) transition metal dichalcogenides (TMDs), with their ultra-thin body, excellent electrostatic gate control, and absence of surface dangling bonds, allow for extreme scaling of the channel region without compromising the mobility. New device geometries, such as stacked nanosheets with multiple parallel channels for carrier flow, can facilitate higher drive currents to enable ultra-fast switches, and TMDs are an ideal candidate for that type of next generation front-end-of-line field effect transistor (FET). TMDs are also promising for monolithic 3D (M3D) integrated back-end-of-line FETs due to their ability to be grown at low temperature and with less regard to lattice matching through van der Waals (vdW) epitaxy. To achieve TMD FETs with superior performance, two important challenges must be addressed: (1) complementary n- and p-type FETs with small and reliable threshold voltages are required for the reduction of dynamic and static power consumption per logic operation, and (2) contact resistance must be reduced significantly. We present here the underlying strengths and weaknesses of the wide variety of methods under investigation to provide scalable, stable, and controllable doping. It is our Perspective that of all the available doping methods, substitutional doping offers the ultimate solution for TMD-based transistors. [ABSTRACT FROM AUTHOR]

We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9 V, an ION/IOFF ratio of 104. The subthreshold slope was estimated to be around 0.9 V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps Dit ∼ 1.2 × 1013 cm-2 eV-1. Comparisons are made with both vertical Si and horizontal SiGe FETs performances. [ABSTRACT FROM AUTHOR]