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Neural networks are achieving state-of-the-art performance in many applications, from speech recognition to computer vision. A neuron in a multi-layer network needs to multiply each input by its weight, sum the results and perform an activation function. This paper is an extended version of the article in which we present an implementation of an amplifier-based MOS analog neuron and the optimization of the synaptic weights using in-loop circuit simulations. In addition to the base topology, we present two variations of the original conference paper topology to reduce area and power. MOS transistors operating in the triode region are used as variable resistors to convert the input and weight voltage to proportional input current. To test the analog neuron in full networks, an automatic generator is developed to produce a netlist based on the number of neurons on each layer, inputs, and weights. Simulation results using a CMOS 180 nm technology for all topologies demonstrate the neuron proper transfer function and its functionality while trained in test datasets.

SPICE has been the corner stone of integrated circuit simulation since the 1970s. The device-level options that are available for SPICE/analog simulators to simulate a circuit netlist are typically compact models and/or Verilog-A structural and behavioral models. Though these simulations are very accurate, for large and complex circuits/systems they are extremely slow and even computationally infeasible. Thus, as a paradigm shift of the conventional design simulation flow, this paper presents a complete Simscape®based design and simulation flow for ultra-fast design exploration of graphene based nanoelectronic systems. A behavioral model for a dual gate graphene field effect transistor (GFET) is modeled in Simscape®based on the drift-diffusion conduction mechanism. The kink region of the $$I-V$$I-V characteristic is modeled via a displacement current. For case study design circuits, an all graphene based low noise amplifier and an LC-tank voltage controlled oscillator are presented. The results show that the proposed design alternative to simulate analog circuits and systems is a viable option in addition to the existing SPICE, VHDL-AMS or Verilog-A based flows and can open the way to true device-level system design exploration and optimization. To the best of the authors' knowledge, this is the first ever paper to explore a Simscape®model of a GFET device and design a GFET based radio-frequency circuit using Simscape®.

Modern consumer electronics are designed as analog/mixed-signal systems-on-chip (AMS-SoCs). In an AMS-SoC, the analog and mixed-signal portions have not received systematic attention due to their complex nature and the fact that their optimization and simulation consume significant portions of the design cycle time. This paper presents a new approach to reduce the design cycle time by combining accurate polynomial metamodels and optimization algorithms. The approach relies on a mathematical representation (metamodel or surrogate model) of AMS-SoC subsystems/components. Polynomial metamodels are created from post-layout parasitic netlists and provide an accurate representation for each figure-of-merit over the entire design space of the AMS-SoC component. The metamodel approach saves a very significant amount of time during design iterations. Polynomial metamodels are reusable and language independent. Three algorithms are investigated to compare the speed for optimization on the polynomial metamodels. Two widely used circuits have been designed in two different technologies as comparative case studies: an 180 nm LC-VCO and a 45 nm ring oscillator (RO). Experimental results prove that the metamodel-based optimization achieved speed-up as high as 21,600 $$\times$$ × for the LC-VCO circuit and 11,750 $$\times$$ × for the RO in comparison to the actual circuit netlist-based (SPICE) optimization, with less than 1 % error. Thus, the paper demonstrates that the polynomial metamodeling approach to the design problem is an effective and accurate means for fast design space exploration and optimization.

This paper presents the author's integrated approach to custom device mismatch simulations, and is intended for both the design and the modeling communities. It provides the means for the generation of Monte Carlo mismatch models, when foundry libraries are insufficient. This is done by presenting an overview of matching for practically every device of interest in analog design and a strategy for fitting measured data to custom models. Mismatch modeling subcircuits are presented for an array of different simulating environments and bias conditions. Results from silicon are used to back and build confidence on the approach. Furthermore the solution to many CAD or simulator shortcomings is introduced and a number of useful scripts (performing all the necessary netlist/library modifications) is presented.

Due to the ongoing growth of microsystems' complexity, there is an urgent need for automatic optimization. In order to include it seamlessly in the customary design process, the algorithms have to be fast and robust. Calculations of the quality function call for at least one FEM-, netlist based or behavioral simulation. Thus the optimization process is a very time consuming task. This paper presents a methodology for enhancing the convergence characteristics of heuristic search methodologies. The concept is to combine direct optimization strategies with interpolation methods in such a way that a mathematical model of the quality function is successively constructed in parallel to an optimization run. Once this model has is meaningful enough, its evaluation can substitute time consuming simulation runs.

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 μm CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 μm by 2134.2 μm and ±5 volt power supply.

The implementation of a VHDL-AMS to SPICE converter (Vhdl2Spice) to be inserted in a complete CAD environment [1] is described. Vhdl2Spice generates a SPICE netlist by tracing down the VHDL IIR par...

In this paper a brief overview of the electro-thermal simulation based on the method of simultaneous iteration is given, through the example of the SISSI (Simulator for Integrated Structures by Simultaneous Iteration) package. The modular approach used for the layout-based electro-thermal netlist generation is described. This approach allows an easy implementation of package model libraries. The capabilities of SISSI are introduced by simulation examples where in most cases the results are compared to measurement results.

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular, signal crosstalk through the common chip substrate has become increasingly problematic. This paper demonstrates a methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. First, a triangular discretization method is employed to generate RC equivalent-circuit substrate models which are far less complex than those formulated by conventional techniques. The networks are then accurately approximated for subsequent analysis by an efficient reduction algorithm which uses a well-conditioned Lanczos moment-matching process. Through congruence transformations, the network admittance matrices are transformed to reduced equivalents which are easily post-processed to derive passive, SPICE-compatible netlist representations of the reduced models. The pure-RC properties of the extracted substrate networks are fully exploited to formulate an efficient overall algorithm. For validation, the strategy has been successfully applied to several mixed-signal circuit examples.

An integrated software system that facilitates the design, and integrated-circuit layout of continuous-time OTA-C filter biaquad-based structures with typical cutoff frequenceis for a 3µmtechnology in the 500 kHz-8 MHz range is described. The proposed integrated software system consists of three separate software modules written in the C language for the Apollo workstation (DN3000). The first module is a general filter approximation package. This program can approximate conventional magnitude, arbitrary magnitude, arbitrary group delay equalizer, arbitrary magnitude with group delay specifications. The second module aides in the synthesis of the biquad-based OTA-C filter structures. This module is unique in that the C code has the rule-based language CLIPS embedded within the code, and takes into account OTA-C filter nonidealities. An expert system using CLIPS was developed to select an appropriate OTA-C filter structure based on the nonidealities of the structures. After the filter structure has been chosen, the program will guide the user in the calculation of the capacitor values. These calculations are based on the nonidealities of the OTAs included in the standard cell library for layout, in addition the design of special purpose OTA as another alternative is also considered. Furthermore, the program will develop the necessary input files for the layout generator. The final module is a modified version of AIDE2, a standard cell layout generator for switched-capacitor circuits. The input files to the modified AIDE2 is a C language program that describes the circuit (i.e., standard cells and their netlist). The output file is a CALTECH Intermediate Format (CIF) file that is required for fabrication.