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FitzHugh-Nagumo, FHN, is a most critically significant Neural Cell method which is effectively capable of modeling the synaptic behavior by leveraging van-der-pol oscillators. The FitzHugh-Nagumo model makes use of common circuitry of FHNs, remarkably similar to the very conventional LC oscillators. Conventional LC oscillators, needless to say, have been largely deployed and comprehensively studied for quite some time. Notwithstanding its similarity to other LC oscillators, FitzHugh-Nagumo contains a resistor in series with the circuit that makes it inconsistent with other LC oscillator models. In this paper, a productive circuit technique is used to make FitzHugh-Nagumo circuit analogous to a LC conventional oscillator, which consequently provides the capability of using analytical approaches on these systems. This gives the designer of neural cells the opportunity of taking advantage of the vast knowledge about oscillatory systems. The proposed circuit model has been verified in terms of accuracy and compatibility for free-running, locked, and unlocked states. In addition, a theoretical analysis, aiming to clarify the background principle of the FitzHugh-Nagumo design process, is also provided. The simulation results which are performed using TSMC 180 nm CMOS technology represent a good agreement between theory and simulation. [ABSTRACT FROM AUTHOR]

In this paper, a digital processor is presented for full calibration of pipeline ADCs. The main idea is to find an inverse model of ADC errors by using small number of the measured codes. This approach does not change internal parts of the ADC and most known errors are compensated simultaneously by digital post-processing of the output bits. Some function approximation algorithms are tested and their performances are evaluated. To verify the algorithms, a 12-bit pipelined ADC based on 1.5-bit per stage architecture is simulated with 1%-2% non-ideal factors in the SIMULINK with a 20 MHz sinusoidal input and a 100 MS/s sampling frequency. The selected algorithm has been implemented on a Virtex-4 LX25 FPGA from Xilinx. The designed processor improves the SNDR from 45 to 69 dB and increases the SFDR from 45.5 to 90 dB. The calibration processor also improves the integral nonlinearity of the ADC. [ABSTRACT FROM AUTHOR]

This paper presents a new high-speed CMOS 4-2 compressor which is an essential part in fast digital arithmetic integrated circuits. Current-mode techniques have been used to improve the overall performance of the compressor. New fully differential proposed circuit improves speed up to 45% also reduces occupied area in comparison to other high-speed conventional compressor circuits. To evaluate the performance of the proposed circuit, two other structures have been chosen and all of the circuits have been simulated in 0.18 μm standard TSMC CMOS process with 1.8 V power supply voltage. [ABSTRACT FROM AUTHOR]