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This paper applies the phase conjugation method which is equivalent to time reversal in the time, to wireless power transfer using two different retrodirective array configurations: linear uniform transmitting array and non-planar random transmitting array. The method is based on the reciprocity property of the wave equation. The idea is validated by employing 10 transmitting retrodirective antenna array (Tx) placed on the walls of a cubical room and one receiving antenna (Rx) in free space. In the retro-reflective beamforming, wireless power transmission is guided by pilot signals. The Rx broadcasts pilot signals to its surroundings, and based on analyzing these signals, a wireless power transmitter delivers focused power beam onto the Rx. The study is performed for line of sight and non-line of sight (NLOS) locations for the Rx. We calculate the received (Rx) power for different array configurations, and the power flow density inside the room. Simulation results show that applying the reciprocity theorem in both configurations provides significant enhancement in power transfer system efficiency at different Rx locations. Furthermore, results demonstrate that the power beam in reaction to the pilot signal is capable of tracking the mobile device's location dynamically even if it resides in a NLOS location. When the wireless power receiver resides in the far-zone, a linear array and a random array produce the same power level at the near-zone focal point, but the maximum far-zone gain associated with the random array is on the average 1.5 dB lower than that of the linear array. [ABSTRACT FROM AUTHOR]

This paper investigates wireless power transmission (WPT) system efficiency of antenna arrays in free space and in fully enclosed boxes with reflecting walls. In this study we investigate the WPT approach for both a uniform transmitting antenna array and a random array. Specifically, we consider 10 transmitting antennas (Tx) placed on two opposite walls of a cubical room and one receiving antenna (Rx) centered in the middle. We calculate the received (Rx) power for different array configurations. Simulation results show that randomness and the presence of reflecting walls provide significant enhancement to the system's power transfer efficiency compared to the maximum efficiency achievable with a similar configuration in free space. Furthermore, the simulated power flow density shows multiple hotspots in space, making the system very dynamic with the advantage of random array over the linear array. This enables power delivery to a moving receiver and meets the demand of harvesting the wireless energy to charge or power up multiple devices at the same time. [ABSTRACT FROM AUTHOR]

This paper presents analysis, characterization and measurement results in a 65 nm CMOS process for different inverter topologies that use various leakage reduction methodologies. The measurement results are carried out to compare the topologies in regards of leakage reduction, active power and speed. Four different methodologies are implemented: standard CMOS, 2-stacked, body biasing, and dynamic logic suppression (DLS). The measurement results indicate that the DLS is an excellent option for ultra-low power IoTs where the leakage is minimized, however, it has a limitation in terms of performance. This makes it suitable for always-on power domain. On the other hand, a standard inverter is a good option for high performance devices but it has the highest leakage which makes it feasible for run fast and stop operation mode. Moreover, stacking and body biasing support low leakage power and moderate performance. The impact of voltage scaling is the best for the DLS where the leakage is saved by 12 × at room temperature. Further, the impact of the temperature increases the leakage current for DLS by 3.5 × but increases by 13 × and 15 × for standard and stacking methodologies, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a built-in-self-calibration RF amplitude detector circuit in 65 nm CMOS is presented. The proposed architecture makes use of two detector replicas with a feedback control system to perform the self-calibration. The system is capable of detecting RF peak amplitudes range of 0–0.6 Vp with a conversion gain of − 3 V/V. The proposed system has a wide dynamic range that can auto-corrects the RF detector to less than 10% across process and temperature variations. This architecture is implemented in standard 65 nm 1P7 M CMOS process. Comprehensive silicon measurement results show that the self-calibration structure improves the detection error of the non-calibrated RF amplitude detector by a maximum of 71% at only 230 μW overall power consumption. The proposed system can be used to calibrate the variations in circuits within an RF transceiver such as LNA, Mixers, oscillators etc. [ABSTRACT FROM AUTHOR]

The electrocardiogram signal (ECG) has been widely used as a diagnostic tool for many heart related diseases. In this work, we present a novel method for the prediction and detection of ventricular arrhythmia using a unique set of ECG features extracted from two consecutive cardiac cycles. Two databases of the heart signal recordings from MIT Physionet and the American Heart Association were used as training, test, and validation sets to evaluate the performance of the proposed method. Linear Discriminant Analysis was used to differentiate between normal and abnormal ECG signals. The discriminatory properties of the ECG features were evaluated by many k-fold cross validations. The proposed method achieved: an accuracy of 99.1%, sensitivity of 98.95%, precision of 98.39%, and area under the receiver operating characteristics curve of 99.97% on the out-of-sample validation data by tenfold cross validation with 5 s window size. Furthermore, the method was capable of predicting the onset of ventricular arrhythmia up to 3-hours earlier; this is the earliest prediction interval compared to any published work so far. [ABSTRACT FROM AUTHOR]

Local feature detection and description algorithms such as scale invariant feature transform (SIFT) algorithm are among the most commonly used techniques in computer vision. They are used mainly to detect and extract high-level information from low-level (pixel) information in images. These algorithms are computationally intensive and its pure software implementations are far from reaching real-time performance especially on embedded systems with limited computational power. In this paper, an Application-Specific Integrated Circuit (ASIC) implementation of the SIFT algorithm is proposed that is suitable for real-time image processing. In the Gaussian scale space generation step, several techniques were used to substantially reduce the hardware complexity: the multiplierless multiple constant multiplication, the symmetrical property of Gaussian mask in addition to the common sub expression elimination algorithm. Through the re-arrangement of SIFT's 128 values in a specific approach, a new multi-ported memory is implemented to reduce the memory size. Furthermore, a novel mechanism is applied to continuously monitor the active window in the input and the intermediate results. The proposed technique does not only improve the performance of the SIFT implementation, but it also keeps the features extraction accuracy exactly the same as the software implementation. In this work, for an image size of 256 × 256 a frame rate of 56 fps was achieved. Additionally, the results confirm that the proposed architecture has lower hardware and memory costs compared to other works in the literature (FPGA based implementations). Lastly this architecture was implemented using Standard Cell Library Based ASIC flow using 65 nm low power GF library, it occupied an area of 1.4 mm 2 and consumed a total power of 30.4604 mW which makes it very suitable for integrated System on Chips (SoC) applications. [ABSTRACT FROM AUTHOR]

ElectroCardioGram(ECG) bio-sensors are used to detect and transmit the electrical activity of the heart over a period of time. The ECGs are treated by a signal processing unit inside the bio-sensor to detect and identify heart related medical conditions. Testing and verification of bio-sensor is of paramount importance as faults in these critical systems may lead to loss of life. However, due to the complexity of these systems traditional testing methods might not be adequate to provide high level of assurance about the correctness of their operation. In this paper, we propose a verification framework where we utilize simulation and formal methods to validate the correctness of the ECG bio-sensor. The framework is used to verify ECG bio-sensor at several levels of abstractions, including the signal processing level, where the ECG signal attributes, signal processing algorithm including its filters, detection and analysis algorithms, and triggering the alarm are modeled. [ABSTRACT FROM AUTHOR]

A phase-based delta-sigma (ΔΣ) analog-to-digital converter (ADC) is proposed and the idea is demonstrated using two architectures. The first architecture adopts a delay-locked-loop (DLL) mechanism. It is realized by a modification of a DLL using a voltage-controlled delay line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ΔΣ ADC achieved 50.5 dB SNDR or 8.09 bits resolution for a 10 MHz signal bandwidth. The second architecture adopts a combination of voltage-controlled and digitally-controlled delay lines (VCDL-DCDL) as the phase-domain counterparts of an ADC-DAC in a traditional delta-sigma modulator. Simulation results of the new modulator achieve a 57.8 dB SNR, or a 9.28 bit over a 10 MHz bandwidth. [ABSTRACT FROM AUTHOR]

Continuous rise in the number of users as well as the increased requirement of bandwidth per user has created a need to use the spectrum efficiently. Cognitive radios are solutions proposed to address the problem of using the spectrum efficiently. Regulatory bodies around the world, FCC included, have introduced specifications intended for cognitive radio applications. TV White Space devices, which operate in the spectrum holes caused by transition from analog to digital transmission, were the first targeted applications for cognitive radio specifications (IEEE 802.22, ECMA-392). However, to maximize the potential of the idea of cognitive radios it is desirable to be able to sense the spectrum across a wide band and accordingly transmit 'smartly'. This paper presents a possible transceiver architecture meant for integrated solutions while providing tentative block level specifications for the proposed architecture. Existing spectrum sensing techniques are discussed and an integrated low power system architecture at the PHY level suitable for waveform-based spectrum sensing technique that utilizes co-operative spectrum sensing methods is proposed. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the editor discusses various reports within the issue on topics including the cancellation of interference in long-term evolution (LTE), graphic processing units (GPUs), and performance evaluation of cognitive radios (CRs).

In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of −13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm × 0.44 mm. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the editor discusses various articles within the issue on topics including network simulation model framework for software defined radio, comparison of long term evolution (LTE) channelizers and Euclidean direction search algorithm for adaptive filtering.

An introduction is presented in which the editor discusses various reports within the issue on topics including baseband processing in Software Defined Radio (SDR) systems, strategies for SDR's antenna design, and the use of power fingerprinting for SDR integrity assessment.

The article announces the retirement of Erik Bruun as regional editor-in-chief of the journal "Analog Integrated Circuits and Signal Processing" for the Europe, Africa and Middle East region.

People who the author would like to thank for their assistance in the creation of journal "Analog Integrated Circuits & Signal Processing" are mentioned.

An introduction to the journal is presented in which the author discusses the 20th anniversary of the journal.