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The paper presents selected elements of logic synthesis of low power FSM. Authors focus on the problem of low power coding for internal states. Proposed coding algorithm leads to reduction of the number of switches and as a result reduction of dynamic power consumption. The paper shows, that effective coding algorithm is insufficient for effective FSM synthesis. A vital role in logic synthesis plays technology mapping. This process requires appropriate function decomposition. The paper presents methods of carrying out technology mapping which uses triangle tables. This method leads to appropriate decomposition path. The experimental results show that effective states coding must be associated with effective technology mapping. [ABSTRACT FROM AUTHOR]

A new, efficient technology mapping method of FSMs, dedicated for PAL-based PLDs is proposed. The essence of the method consists in searching for the minimal set of PAL-based logic blocks that cover a set of multiple-output implicants describing the transition and output functions of an FSM. The method is based on a new concept of graph: the Graph of Excitations and Outputs. The proposed algorithm was tested using the FSM benchmarks. The obtained results were compared with the classical technology mapping of FSM. [ABSTRACT FROM AUTHOR]

A new low power state assignment algorithm is proposed in this paper. The essence of new coding is dividing all the states into subsets, which are sequentially assigned to the individual bits of code. This type of decomposition encoding, in which the coding is done bit by bit, retains the flexibility of assigning code words from the beginning to the end of the encoding process. The results of the experiments confirm efficiency of the proposed algorithm in comparison with the state assignment algorithms that have already been developed. [ABSTRACT FROM AUTHOR]