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The continual downward scaling of devices and increases in drive current have required an ever shrinking interconnect pitch and higher current densities. In order to overcome both the higher signal delay, as well as reliability concerns, new metallization technologies like Cu interconnects and low-k interlevel dielectrics have been developed. The implementation of inlaid Cu interconnects introduces a new set of material systems and geometries which results in new mass transport and failure mechanisms under electromigration. This study focuses on the characterization and understanding of electromigration-induced failures in advanced, 0.13 μm technology node Cu interconnects. Statistically based methodologies, using multi-link test structures, were developed and used to further understand the reliability of these advanced interconnects. Single-inlaid structures designed to test both the upper and lower interfaces associated with a Cu via were used to understand the role of void formation and interconnect geometry in EM behavior. These statistical methodologies were also applied to EM tests on dual-inlaid test structures in order to understand the impact of a continuous via-metal connection on void formation including the potential for multiple failure modes. Dual-inlaid integrations of varying maturity levels were examined to highlight the advantages of the statistically based methodology in determining extrinsic failure modes as well as increasing the confidence of EM lifetime prediction. © 2004 American Institute of Physics [ABSTRACT FROM AUTHOR]