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Modern integrated circuits can contain transistors smaller than 100 nm and gate oxides as thin as 2 nm. As a 0.1 nm decrease in oxide thickness can lead to an order of magnitude increase in leakage current, precise measurement of the oxide thickness is critical. We find annular dark field (ADF) imaging in a scanning transmission electron microscope to be a useful method of independently measuring the thickness and roughness of a gate oxide. Thickness measurements are still possible in cross-sectioned samples as thick as 600 nm. Electron energy loss spectroscopy (EELS) performed simultaneously with the ADF imaging allows the chemical and electronic structure of both conventional and high-k gate dielectrics to be mapped at the atomic scale. The electrical transition region from Si to SiO[sub 2] is seen to occur over a region that is 0.3-0.4 nm wide, even when the structural transition is atomically abrupt. Consequently, a 0.7 nm thick gate oxide would not retain any bulk-like electronic structure. [ABSTRACT FROM AUTHOR]