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In order to protect high voltage direct current (HVDC) system from destructive consequences caused by fault current, a novel concept of HVDC system fault current limiter (DCSFCL) was proposed previously. Since DCSFCL is based on saturable core reactor theory, iron core becomes the key to the final performance of it. Therefore, three typical kinds of soft magnetic materials were chosen to find out their impact on performances of DCSFCL. Different characteristics of materials were compared and their theoretical deductions were carried out, too. In the meanwhile, 3D models applying those three materials were built separately and finite element analysis simulations were performed to compare these results and further verify the assumptions. It turns out that materials with large saturation flux density value Bs like silicon steel and short demagnetization time like ferrite might be the best choice for DCSFCL, which can be a future research direction of magnetic materials.

To develop mechanical circuit breaker in high voltage direct current (HVDC) system, a fault current limiter is required. Traditional method to limit DC fault current is to use superconducting technology or power electronic devices, which is quite difficult to be brought to practical use under high voltage circumstances. In this paper, a novel concept of high voltage DC transmission system fault current limiter (DCSFCL) based on saturable core was proposed. In the DCSFCL, the permanent magnets (PM) are added on both up and down side of the core to generate reverse magnetic flux that offset the magnetic flux generated by DC current and make the DC winding present a variable inductance to the DC system. In normal state, DCSFCL works as a smoothing reactor and its inductance is within the scope of the design requirements. When a fault occurs, the inductance of DCSFCL rises immediately and limits the steepness of the fault current. Magnetic field simulations were carried out, showing that compared with conventional smoothing reactor, DCSFCL can decrease the high steepness of DC fault current by 17% in less than 10ms, which verifies the feasibility and effectiveness of this method.