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The Versatile Video Coding standard was finalized by the Joint Video Exploration Team in July 2020 and is currently considered the state-of-the-art video compression technology. VVC significantly improves coding efficiency compared to HEVC thanks to several new features and tools that incur a large increase in computational cost. This paper presents a complexity and coding efficiency assessment of VVC divided into three analyses, focusing on: (1) the impact of using SIMD optimizations in the VVC Test Model software, (2) the impact of limiting partitioning structures when encoding, and (3) the computational cost associated to each encoding tool in VVC. Experimental results show that SIMD optimizations accelerate the encoding time by 40%, on average, and that limiting the available partitioning structures can decrease encoding time between 40% and 73%. The software profiling revealed that inter-frame prediction is responsible for almost half of the total encoding time. Finally, the paper also presents an analytic discussion on tools and partitioning possibilities that are rarely chosen in the mode decision process despite their high impact in coding complexity.

Harvesting energy from environments has been a promising approach to power ubiquitously distributed Internet of Things (IoT) devices. For harvesting kinetic energy with piezoelectric transducers, synchronized switch harvesting on capacitors (SSHC) rectifiers have been demonstrated to achieve high energy extraction performance without using any inductor. In previous studies, the switched capacitors in SSHC rectifiers are chosen equal to the inherent capacitance of the piezoelectric transducer (PT) to achieve good voltage flip efficiencies at 33.3%, 50% and 66.7% for 1-, 2- and 4-stage SSHC rectifiers, respectively. However, with much larger switched capacitors and the same SMD package size, this paper finds that the voltage flip efficiency can be further increased to 50%, 66.7% and 80% for 1-, 2- and 4-stage SSHC rectifiers, respectively; as a result, the output power can be greatly increased. This paper also finds that the proposed design only requires half number of capacitors to achieve the same voltage flip efficiency for conventional SSHC rectifiers, which significantly reduces the system form factor for miniaturization.

A high-speed comparator constituted by a backgate-input latch and a pre-amplifier is proposed in this paper. Instead of using extra input transistors as in a classic StrongARM latch, the back-gate-input technique proposed in this paper obviates the need for extra input transistors in the latch stage, thus greatly reducing the parasitic capacitance and improving the comparator speed. Unlike the StrongARM latch where the amplification phase begins only after the CLK rises, the amplification phase in this paper begins before the CLK rises and replaces the reset phase, further improving the comparator speed. The pre-amplifier provides a gain of 22-dB, in order to suppress the input-referred noise and offset of the comparator. Designed in the same 22nm Silicon-on-Insulator (SOI) CMOS process for the proposed comparator and the conventional comparators, post-layout simulation results show that the performance in speed and input-referred noise are improved by 22% and 43%, respectively.

The performance of silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is better than silicon devices in terms of switching speed, switching loss and temperature tolerance. Due to the higher di/dt and dv/dt during the switching process and the combined effect of various parasitic parameters, serious bridge-leg crosstalk will be generated in the SiC MOSFET bridge circuit. This paper firstly analyzes the mechanism of crosstalk, and based on the parameters extracted from the device data sheet and experiments, the maximum values of the bridge-leg crosstalk voltage under different operation conditions are calculated. Secondly, a passive Miller clamp circuit on crosstalk suppression in SiC MOSFET bridge-leg configuration is proposed in this paper. When the crosstalk occurs, the proposed driver circuit shunt the Miller current to the ground, and the gate-source parasitic capacitance of SiC MOSFET is bypassed. The advantages of the proposed crosstalk suppression circuit are that the switching speed is not sacrificed, the circuit topology is relatively simple, and it is easy to be integrated into the driver circuit of SiC MOSFETs. Finally, experimental results prove the effectiveness of the proposed crosstalk suppression circuit.

To alleviate the dependence on sensor quality and to reduce the accumulated error in traditional inertial navigation systems, this paper proposes RUPT: a millimeter-wave radar aided pedestrian dead reckoning system with dual foot-mounted inertial measurement units (IMU). RUPT in this paper is a comprehensive data processing procedure which pre-processes both inertial data and millimeter-wave data and fuses them in a complementary way. Extensive experiments have demonstrated that the accuracy of RUPT has been improved by up to 65% over the conventional dual-foot mounted pedestrian tracking system.

In recent car developments, the proliferation of Communication systems with several electronics nodes results in increased cost, complexity, and wire harness weight. Such nodes are usually connected by several wires, like a differential communication bus, power supply lines, and possibly addressing lines. In this paper, novel transmitter designs for reducing the amount of interconnects between the nodes are proposed, exploting communication on the power lines, occupying unused parts of the spectrum. Besides the cost-saving, such methods reduce the automotive harness complexity and lead to more flexible solutions, lowering the demand for raw material and consequently reduced emissions during the production process. However, this requires adding specific sections to apply communication to the power line in each IC devices controlling the nodes. In this paper, some 180nm HV-CMOS SOI transmitter solutions are proposed to operate a data rate of up to 2Mbps. Extended simulations in an automotive environment model validate and compare the proposals.

This paper proposes BER evaluation system that evaluates BER of TLC and QLC NAND flash memories with reliability information such as write and erase (W/E) cycle and data-retention time by combining SSD model emulator and device characteristics of NAND flash memories. Proposed system decides which ECC type should be used in TLC and QLC NAND flash in SCM/TLC/QLC NAND flash tri-hybrid SSD, corresponding to various applications and memory capacity ratio. For hm_0 (write- cold application), BCH ECC is enough to correct bit errors in TLC NAND flash. On the other hand, for prxy_0 (write-hot application), LDPC ECC must be applied to TLC NAND flash in case of small SCM capacity, large W/E cycles and high BER in TLC NAND flash. In contrast, this paper concludes that QLC NAND flash needs LDPC ECC regardless of application and memory capacity.

This paper presents a time-of-flight (ToF) CMOS image sensor with pulse-frequency-modulation (PFM) pixel for in-pixel code discrimination (CD). One of ToF's main problem is interference between multiple sensors or malicious one by third party. CD is a function that discriminates signal light from the others with code modulation, which will be an effective countermeasure against such interference. Proposed pixel contains a PFM circuit and counters, with which in-pixel CD and distance measurement (DM) is tried to be realized. In this paper, methods of CD and DM, circuit implementation are shown, and HSPICE and C simulation demonstrates signal-to-background ratio rejection of -7dB and 8dB signal-to-interference ratio for 128-bit CD with less than 0.08% error.

An integrated circuit (IC) for decoupling of multiple-input multiple-output (MIMO) antennas as well as for aperture and impedance tuning is demonstrated in this paper. The IC decouples the adjacent stripes of the inverted-F antenna (IFA) forming the two separate IFAs for MIMO operation in middle- and high-cellular frequency bands. For low-band operation the IC joins the stripes, forming a single IFA with double the physical length. The same IC is also used for impedance and aperture tuning of the antennas. The IC is designed and fabricated in dedicated 130 nm RF switch technology. The design and measurement results are presented in the paper.

Modular multilevel converters (mmcs) are the basic building blocks of multi-terminal direct current systems (mtdcs). The current rapid growth of such systems makes it imperative to develop methods to analyse their dc-side stability, thereby ensuring a correct overall operation. In this paper, starting from a simplified mmc model, general conditions for dc-side stability are derived. These conditions have been validated by simulating a point-to-point high voltage direct current system and an mtdc network. mmc models of different degrees of accuracy have been adopted to show that the conditions derived in the paper hold with a good degree of approximation even when more detailed representations are considered.

The increasing density of Multiple-Input Multiple-Output (MIMO) arrays in imaging radars for the automotive industry demands highly parallel systems with low-footprint accelerators, which would enable the concurrent processing of a high number of virtual channels with a low-latency, and without a high area overhead. In this paper, we design, implement, and test multiple handcrafted compression schemes for Twiddle Factor (TF) Read-Only Memories (ROM), aiming to reduce the footprint of a variable-length and dual-radix Fast Fourier Transform (FFT) accelerator in a Multi-core Digital Signal Processor (DSP) for Frequency Modulated Continuous Wave (FMCW) radars. The compression schemes proposed in this paper involve double delta encoding, Radix-specific address optimizations per port, symmetry inclusion, and exploitation of the bit resolution changes within the radar processing chain. All schemes are verified in an FPGA in terms of logic utilization and quantization using a 77-GHz radar, and implemented in a RISCV-based Processing Element (PE) of a Multi-core DSP with an Adaptive Body Bias (ABB) approach in 22FDX technology for assessing area, leakage, and relative latency savings when compared with a dual-ROM equivalent in the state-of-the-art.

In the mordem society, physical infrastructure and information technology are inseparable. The concept of cyber-physical systems (CPSs) is then proposed and has been widely concerned by researchers in recent years. Various models have been introduced to meet the actual needs. In one type of those models, the physical part and the cyber part are coupled and influence each other. The cyber part monitors and controls the physical part, but at the same time it may also bring certain harm; the fault in one part may also be transmitted to the other and affect the performance of the counterpart. Here, this paper introduces an asymmetric interdependent model and studies how the coupling pattern of CPSs affects the system robustness. In addition, the coupling pattern of CPSs is optimized by using the simulated annealing (SA) algorithm to reduce the performance loss. The results of this paper may find applications in the future CPS planning.

With the rise of the Internet of Things (IoT), a huge market for so-called smart edge-devices is foreseen for millions of applications, like personalized healthcare and smart robotics. These devices have to bring smart computing directly where the data is generated, while coping with the limited energy budget. Conventional von-Neumann architecture fail to meet these requirements due to e.g., memory-processor data transfer bottleneck. Memristor-based computation-in-memory (CIM) has the potential to realize smart local computing for highly par­allel data-dominated AI applications by exploiting the inherent properties of the architecture and the physical characteristics of the memristors. This paper provides a broad overview of CIM architecture highlighting its potential and unique properties in enabling smart local computing. Moreover, it discusses design considerations of such architectures including both crossbar array as well as peripheral circuits; special attention is given to analog-to-digital converter (ADC), as it is the most critical unit of analog-based CIM operation e.g., vector-matrix multiplication (VMM). Finally, the paper outlines the potential future directions for CIM-based edge smart computing.

This paper presents a single-aperture, single-pixel reader for communication with Optical Frequency Identification (OFID) tags. OFID tags use solar cells to transmit and receive information wirelessly as well as to harvest radiant energy. Due to its single-aperture architecture, the reader's optical system provides a shared optical path for reception and transmission. Also, physical alignment between the reader and an OFID tag is visually guided using the reader's emitted light, securing a robust data link as long as the OFID tag is illuminated. In this paper, a description of the reader's optical and electronic sub-systems are presented. The transmitter and receiver circuits are described in detail. The transmitter, built with a linear LED driver, achieves a power efficiency of nearly 87%. The receiver, featuring a third-order bandpass filter, reduces both low-frequency and high-frequency ambient noise. A prototype of the reader was fabricated and housed in a custom 3D-printed enclosure. Test results show that the reader is able to receive modulated luminescent signals from an OFID tag at a distance of 1 m and at a data rate of 3 kbps.

This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89μΑ to 1.46μΑ. By connecting ternary inverters back-to-back, a trit-storage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.

This paper proposes a methodology based on machine learning to find apparent causal relations between performance targets and design variables in analog circuits. Diversified filtering and wrapping variable selection algorithms are utilized to construct a causal graph that identifies the major circuit design parameters that can be used to optimize the performance of analog circuits. Based on the constructed causal graph, a sequence of design procedures can be extracted and followed to optimize the performance of a design. The proposed methodology is validated using a two-stage op-amp. The obtained causal graph agrees with analytical design equations published in the literature for the selected two-stage op-amp. The results also show that the proposed methodology can accelerate the circuit design process and effectively help designers understand the reasoning behind different design decisions.

To increase the energy extraction capability and thus improve the power efficiency, it is critical to reduce the energy loss of interface circuit in the energy harvesting (EH) system. The synchronized multiple bias-flip (SMBF) control has been proposed and proved to be highly effective to increase the output power in piezoelectric EH systems. However, many existing designs based on bias-flip suffer from the limitations in real application as the external control or supply are required. Moreover, the control algorithm is often only suitable for a designated transducer and inductor. In this paper, an integrated piezoelectric EH interface circuit with synchronized triple bias-flip (S3BF) has been proposed to flip the voltage across the parasitic capacitor of piezoelectric transducer during the zero-crossing. Meanwhile, the adaptive control of the flipping signal has also been adopted to meet the requirement of different configurations of transducers and inductors. The proposed interface circuit has been designed in 0.18-µm CMOS technology. Without any external control circuit or power supply, it can achieve cold start-up when the external inductances vary from 33 μH to 500 μΒ. When the external inductance is 50 μΒ, the simulated flip efficiency is 87.2 %, and the maximum output power is 17.4 μW, which is 3.4 times of the full-bridge rectifier.

A switched-capacitor (SC) step-down DC-DC converter reconfiguring its open-loop topology based on the input voltage to resolve the efficiency issue of single topology is presented in this paper. An adaptive switch modulation (ASM) technique, modulating switch width of the power stage, and a frequency scaling (FS) technique, scaling the sampling rate of the PFM controller, are also proposed to reduce the quiescent current of the converter for light-load efficiency. The prototype converter in 0.25μm CMOS process with integrated flying capacitors generates a fixed regulated output voltage of 1.8V from an input voltage ranging from 3V to 4.2V. Experimental results show that the gate driving loss and the PFM controller power are decreased by more than 70% with the ASM and FS techniques. The light-load efficiencies are enhanced by 7% and 10% when the input voltage is 3V and 4V, respectively. The transient response time is about 500ns after a step current from 50μA to 10mA. Its power efficiency is high than 70% over a wide load current range with a peak value of 83%.

This paper presents a USB 3.0 based readout platform for real-time ion imaging applications. The front end utilizes an ion-imaging array containing 16 k ISFET pixels to capture ion diffusion at 6100 fps. Operating at 200 MHz, the chip streams ion information at a data rate of 762.94 Mb/s. The backend readout system employs a FIFO-to-USB bridge (FT601Q) that supports Super Speed (5Gbps) to perform real-time data streaming and operates in bulk transfer mode to ensure data integrity. Implemented on a Xilinx Virtex UltraScale+ FPGA, the system involves a high-throughput data path through the on-board DDR4 SDRAMs, based on which a ring buffer is designed to provide the 2 GB buffering capacity. The readout system can operate in real time regardless of the USB glitches encountered on the Windows OS when involving data polling. In addition, a simple differencing algorithm with threshold detection is integrated into the back end for dynamic frame rate operation. The proposed readout system performs real-time ion imaging at high speed as well as streams the collected images for visualization within a latency of 25 ms, achieving state-of-the-art performance for high-speed Lab-on-Chip applications.

Nowadays, hardware-based AES faces more than one type of Side-Channel-Attacks (SCA), such as the Differential Power Analysis (DPA) attack and the Differential Fault Analysis (DFA) attack. However, most of the current DFA-resistant implementations of AES only focus on resisting the DFA attack but with minimal concurrent considerations on their DPA resistance capability. In this paper, we propose a fault resistant AES with DPA awareness. First, we evaluate the DPA resistance for different implementation architectures of AES before the implementation with S-Box over GF(24)2 is selected. Second, we evaluate the DPA resistance for different fault detection architectures before the concurrent fault detection method is selected. Third, we propose a novel fault resistant technique for AES using input-output differential tables over GF(24)2. We have performed tests based on Partial Guessing Entropy (PGE) to evaluate the DPA resistance for the existing DFA-resistant designs and our proposed design. Experimental results prove that our design has a slower convergence speed (around 33%) with a 100% fault coverage rate and less area than the existing countermeasure designs for fault injection. Results also show that the fault detection designs weaken their DPA resistance, which indicates the importance of co-design of DFA and DPA to achieve less power information leakage.

Deep neural network technology is a milestone achievement in the field of computer vision. It obtained the performance that the shallow network cannot achieve through the multi-layer network structure and the learning method of reverse adjustment parameters. However, the feature extraction algorithm of the shallow network is very effective and also is more beneficial for deep neural networks. In this paper, we combine the shallow network algorithm to proposes the gradient local binary pattern layer(GLBP layer) to replace the first layer of Convolutional Neural Networks(CNNs). The GLBP layer plays a role in initializing the CNNs and can improve network performance without increasing the number and complexity of network layers. In the experiment, using the extracted layer modified by the GLBP feature algorithm to replace other classic deep neural networks, 2.65% and 2.9% performance improvements were obtained in the WideResNet16-2 and ResNet-101 respectively when training on CIFAR-100 dataset.

In this paper, we propose and implement a single-electron transistor (SET) based on cobalt oxide for the first time. The SETs were fabricated through nanofabrication process compatible with the CMOS technology. A cobalt oxide (Co1-yO) on the surface of the source (S) and drain (D) Co electrodes is utilized to act as a quantum dot (QD). The diameter of QD is calculated to be 2.3 nm. The interface between Co1-yO and Co thin films (S/D electrodes) is used as tunneling junctions. The SET based on CoO exhibits typical single electron transport characteristics. Owing to the high Coulomb blockade energy (~180 meV), the Coulomb blockade regions still remain at room temperature (300 K), revealing the nanometer scale CoO-based SETs have great potential to operate at room temperature.

Blocks of 3D-NAND flash memory are programmed in order of WL. In real usage of 3D-NAND flash memory, a block contains both programmed WLs and not programmed WLs because the programmed data do not always fill the block. In the block, the last data are programmed at 'last-programmed WL' where the upper WL is not programmed. The last programmed data are supposed to have high reliability owing to shorter data-retention time. However, when upper WL is not programmed, BER of last-programmed WL largely increases because upper WL has less electrons and causes lateral charge migration. To suppress the errors at last-programmed word-line, this paper proposes Last-programmed Word-line Protection (LWLP). Proposed LWLP suppresses BER by 37% at last-programmed WL and extends data-retention time by more than 4 times.

A fundamental problem of text-to-image synthesis is the lack of quality assessment for a single generated image. Quantitative indicators of this work (such as Inception Score and Frechet Inception Distance) only affect plenty of images' feature distribution. It causes monotonous evaluation and plenty of poor-quality image results. This paper proposes a new evaluation criterion for text-to-image synthesis by the blind image quality assessment(BIQA) method. To train the model, a Multi-Metrics Quality Assessment Dataset for generated birds' images(MMQA) is proposed. Besides, the Multi-hyper model is proposed to fit our dataset better. Experiments show that our method evaluates text- to-image tasks more comprehensively and optimize their results.

Since Deep Convolutional Neural Network (DCNN) training involves complex computations and data transmissions, the previous DCNN processors hard to achieve ideal energy efficiency. This paper proposed a DCNN processor supports both inference and training for the embedded system. The processor contains three heterogeneous cores to provide distinct computation patterns and dataflow for different training phases. In addition, since inference takes up more than 90% of the workload of the DCNN application, the three cores of the processor can be reconfigured to efficiently support the inference to achieve leading resources Utilization. The processor is fabricated in 55nm CMOS technology, post-layout simulation shows the processor achieving 1.36 Tops/w energy efficiency for training and 2.44 Tops/w for the inference.

In this paper, a low-power quadrature LC—oscillator using the current-reuse technique is presented. In the proposed topology, both the core-and-coupling currents are reused to reduce the power consumption. A quadrature LC-oscillator is designed in CMOS 65 nm technology for Bluetooth at 2.45 GHz. The oscillator consumes 2.8 mA of current from a 0.85 V supply voltage. The oscillator's simulated phase noise at 3 MHz offset from the 2.45 GHz center frequency is -130.162 dBc/Hz, resulting in a figure-of-merit (FoM) of 184.4 dB.

This paper presents a multimodal neural recording system incorporating reconfigurable neural recording front-ends to improve hardware availability. The proposed neural recording front-end utilizing the reconfigurable signal conveyor based on the folded-current- mirror structure is configured to process either voltage or current input signal, depending on the targeted experiment scenario, given experiment setup, and varying status of the recording environment. Thus, out of the total number of recording channels, how many channels are used for voltage and current recording can be set as desired, which maximizes the flexibility of the experiment and the usefulness of the recording system. The implemented system is successfully applied to the in vivo recording experiment conducted in the hippocampus area of a mouse brain. The neural recording front-end achieves input-referred noise performances of 2.4 µV rms and 5.19 pA rms in the voltage and current recording modes, respectively. The power consumed by each recording channel is 5.718 µW, and only 54 nW is used to operate the reconfigurable signal conveyor.

Face recognition applications are being widely studied owing to their extensive usability in the field of computer vision. However, processing an entire image requires a considerable amount of time. To reduce the processing time, several algorithms that extract only the face from the image during pre-processing are studied. Haar classifiers are extensively used for the hardware implementation of face detection algorithms that improve the processing speed of face classification. This paper proposes a Haar classifier based face detection architecture that removes unnecessary iterations during classification to further improve the processing speed. The proposed architecture improves the processing speed by 4.46% compared to that of conventional Haar classifier based face detection architectures, for face detection using a VGA image with 30 faces. The proposed architecture tends to improve the processing speed as the number of faces in the image increases while matching the detection accuracy of conventional methods. Additionally, this architecture can be widely applied to classification algorithms that are based on iterations.

This paper presents a reconfigurable LDPC decoder implementation fully compliant with all the configurations in the 5G NR standard. Based on the row-based layered normalized Min-Sum (NMS) algorithm, the optimization approaches are proposed to solve the data dependency hazard in the pipeline process. The proposed instruction-level reordering diminishes the redundant latency of our pipelined decoder architecture. Moreover, the proposed data-level rescheduling optimizes the decoding sequence to remove the remaining pipeline stalls in the high- throughput design without decoding performance degradation. Evaluated in Xilinx VCU1525 FPGA, our design achieves a throughput of 6.7 Gbps per iteration. Implemented in TSMC 28nm CMOS process at the post-layout stage, a 33.2 Gbps, in one iteration, throughput can be achieved at a clock rate 556 MHz with the core area 1.97 mm2.

In this paper, the observation of transient negative capacitance signature (NCS) in an organic ferroelectric gate stack (OFEGS) at minimum supply voltage (Vs) of ±0.5 V is investigated employing a well-calibrated Ginzburg-Landau-Khalatnikov (GLK) model in the environment of Sentaurus technology computer-aided design (STCAD). We observe an 88.62 to 94.76 % reduction in the average coercive voltage (Vc) of the proposed OFEGS, which is still a significant challenge for the conventional ferroelectric (FE) lead zirconate titanate. We study the resistor-OFEGS (RC ofe ) series network behaviors in response to a bipolar and unipolar triangular signal. Our findings prove that the presence of NCS is directly correlated with the FE polarization (FEP) switching and not because of any extrinsic defects in the system. The various impacts of Vs, GLK parameters, R, dipole switching resistivity (R ofe ) variations on the NCS response are investigated. The proposed OFEGS can harness the NCS effect at ±0.5 V with minimum energy dissipation of 4.81 × 10-16 J, a challenge for the oxide FE-based gate stacks. Calibrating R to the maximum limit, we can capture the S-shaped ideal Landau path where the NCS is maximum with a small deviation of about ±0.006 V at zero FEP. Finally, an OFEGS based Landau transistor is implemented, providing a minimum subthreshold swing (SS min ) of 38.21 mV/decade, which is 36.32 % lesser than the fundamental SS min limitation of 60 mV/decade. Therefore, the proposed OFEGS with a minimum Vs and remanent polarization (P r =3D 1.244 μC/cm2) could be used as a gate stack for designing sub-60 mV/decade transistor technology.

In the past few years, the demand for computationally intensive applications, such as digital signal processing or convolutional neural networks, has grown exponentially. As they often rely on a significant number of multiply-and-accumulate cells, it is crucial to optimize their area and cost. Recently, a 3D Nanofabric flow has been proposed, where logic circuits are designed by stacking N identical vertical tiers on top of each other. Exploiting identical layers allows a fabrication process similar to the Vertical-NAND flash, where all the layers can be patterned at once. While the 3D Nanofabric flow presents several layout constraints (single metal routing and identical vertical layers), it can decrease the area by around one order of magnitude, leading to area-efficient and cost-effective circuits. In this paper, we propose to use the 3D Nanofabric process flow to design low-area multipliers. As multipliers can be designed using a regular array organization, we show how they can be spread across multiple vertical layers using the 3D Nanofabric flow, while respecting the different layout constraints. We then provide thorough circuit-level evaluations, including parasitics, to showcase the benefits of our proposed 3D multipliers at the circuit-level. We show that by stacking up to 64 layers to build a 64-input bit multiplier, the area and area-delay- product can be decreased by 28.6x and 25.5x, respectively, compared to a traditional 2D implementation using a 28nm FDSOI technology, with only a 10% and 35% delay and power consumption overheads, respectively.

In this paper, we proposed a resource-efficient 'QRS' detector with superior detection accuracy. Inspired by the strategy of the folded architecture, we adopted a reconfigurable time-sharing computation unit with a pipeline schedule. To further precisely locate the position of the 'R' peak and minimize the extra hardware cost, we designed the position calibration unit (PCU) based on the data compression technique. The proposed architecture was implemented on Xilinx Zynq-7000 with Verilog programming language. The proposed architecture achieves a sensitivity, Se of 99.76%, a precision, +P of 99.85%, and a detection error rate, DER of 0.40% on MIT-BIH database, which attains the best performance compared to state-of-the-art designs. Furthermore, the proposed architecture achieves a better hardware efficiency with 13×, 1.28×, and 4.35× reductions in computing resources, storage memory, and power consumption, respectively.

The rapid advancement of intelligent systems, especially robotics and autonomous driving, is highly reliant on low-complexity and high-accuracy stereo matching algorithms. However, the performance of state-of-the-art stereo matching algorithms still has great space for improvement by gaining awareness of the implicit information hidden in the cost volume layers. In this paper, we propose a low-complexity local stereo matching algorithm named Cross-Layer Information Fusion (CLIF), to improve the matching accuracy by exploring the hidden information. First, we analyze and extract the hidden information into an auxiliary extractor using a novel fusion method. Second, we propose an information sharing strategy that transforms the extractor into a regularization term on each cost volume layer. Then we improve the design by re-constructing the information extractor between the adjacent cost volume layers and form a pipelined hardware architecture on the FPGA platform. Experimental results show that the proposed CLIF algorithm improves 6.53% average accuracy incurring negligible resources and performance impacts, compared to the state-of-the-art solutions.

This paper presents a transconductance boosting method with a stacked current-reused inverter-based gain cell for ultra-low power RF applications. For the same bias current, the proposed method can boost the conventional inverter-based amplifier transconductance by twice, an overall quadruple boost compared to a single MOSFET in sub-threshold region. A 65nm CMOS based post-layout level implementation of the LNA including an on-chip matching network shows a 1.3 dB better noise figure as single inverter implementation for the same power of 45 μW. A cross-coupled stacked-gm VCO implementation achieves 44% higher voltage swing as that of the cross coupled single inverter at 74μA current, owing to the doubled gm value.

Soft-output decoder is of great importance to be applied in iterative receivers, of which belief propagation (BP) algorithm has been widely studied for 5G low-density parity- check (LDPC) and polar codes. However, for polar codes, BP decoding suffers from high computational complexity and unsatisfactory convergence. To this end, soft cancellation (SCAN) polar decoder has recently drawn attention from academia and can be further improved by using the bit-flipping strategy. Limited by the serial nature of message propagation, the SCAN flip (SCANF) decoder cannot meet a high throughput. In this paper, we accelerate the decoding speed by the fast processing mechanism, conducting Fast-SCANF decoder. The corresponding hardware architecture is designed with memory optimization and implemented by TSMC 40nm technology, delivering a 2.1 Gbps throughput and 65 pJ/b energy. To the knowledge of authors, this is the first SCANF hardware decoder.

A charge-recycled amplifier-less current-to-digital converter (CDC) is presented in this paper. The highly digital CDC is based on ultra-low-power subthreshold operation, amplifier-free design, scalable current range, and high-resolution digital circuits. It is realized using a mixed-signal approach by utilizing an analog comparator, 6-bits current steering DAC, an implicit passive integrator, and digital signal conditioning circuits. The proposed converter can be operated in tri-modes to support multiple current sensing applications, i.e. Mode1: current range (CR) from 10nA to 400nA, Mode 2: CR from 0.5μΑ to 5μΑ, and Mode3: CR from 2.5μΑ to 42.5μΑ. The proposed CDC is implemented in 180nm CMOS process with an active area of 0.54 mm2 while consuming 11.2μW. It achieves a 77.8dB dynamic range at a bandwidth of 300Hz from 1V supply with an FoM of 114.2fJ/step.

Side-channel attacks (SCA) pose significant threats to the hardware security of embedded devices. Various logical and circuit-level countermeasures propose security, but they all come with different power, performance, and area overhead. Besides countermeasures cannot guarantee security, if the adversaries have enough time and computing power in hacking. Thus, highly accurate, real-time attack detection techniques are needed. This paper proposes a switched-capacitor circuit that can detect power SCAs by intrusion detection of a current sense resistor in the external power supply line. A pulsed current is pulled on the supply line to introduce a voltage difference proportional to the IR drop. This IR drop is then amplified through a parasitic- insensitive switched-capacitor amplifier and compared against a pre-determined threshold. The circuit achieved a 4.01us typical detection time and better than 72% accuracy, consuming 2.97 mW in 65-nm CMOS. This work is the first mixed-signal IC implementation for power SCA detection. Compared to prior approaches that monitor the entire on-chip power grid, this circuit is more computation- and energy-efficient. It uses a single sensor with no need for data mining or machine learning classification.

With the surge in demand for data storage and processing in emerging applications, the traditional CMOS-based Von-Neumann architecture is facing challenges such as memory wall and static power consumption. In order to conquer the above-mentioned bottlenecks in computing systems, computing­in-memory (CiM) architectures based on non-volatile memory (NVM) have been widely researched. In this paper, we propose a CiM paradigm based on spin-transfer torque magnetic ran­dom access memory (STT-MRAM), which combines common read-like mode (RLM) and write-like mode (WLM). On the basis of realizing the basic functions AND/OR/NAND/NOR, our design coordinates the high speed of RLM and the integrity of WLM to perform complex operations like full-adder (FA) and XOR/XNOR. In addition, the high speed and low power consumption of the proposed CiM paradigm are established by circuit-level simulation with a 40 nm design kit.

The liquid state machine (LSM) is a kind of spiking neural network (SNN) that usually is mapped to an NoC-based neuromorphic processor to perform tasks such as classification. The creation of these LSM models does not consider the structure of Network on Chip (NoC) which resulting in heavy communication pressure on the NoC. In this paper, we propose a hardware aware LSM network generation framework. By keeping the communication between neurons within cores as much as possible, this framework could reduce the communication overheads between cores effectively. The experimental results show that the LSM model produced by our framework could achieve state-of-art accuracy and is hardware-friendly. Compared with the mapping method, the synapses in our LSM is reduced by 94.14%, the total packets in NoC is reduced by 78.3%, the maximum transmission latency is reduced by 97.5%, the average transmission latency is reduced by 54%, the throughput increased 2.8x.

Sleep posture, as a crucial index for sleep quality assessment and pressure ulcer prevention, has been widely studied for medical diagnoses and sleep disease treatment. In this paper, an unobtrusive smart mat system for sleep posture recognition is proposed, which is based on a dense flexible sensor array and printed electrodes and along with an algorithmic framework. With the dense flexible sensor array, the system offers a comfortable and high-resolution solution for long-term pressure sensing. Meanwhile, compared with other large-area and low-density mat systems, it reduces the area to minimize manufacturing cost and computational complexity, while also increases the density of the sensor to improve accuracy. To distinguish the sleep postures, the algorithmic framework that includes pre-processing, feature extraction, and posture classification is developed. Pilot studies in two scenarios including subject-dependent and subject- independent classification are performed with 7 persons for 4 different postures recognition. The experimental results show that the accuracy of the smart mat system can achieve over 78% using Support Vector Machines (SVMs) and k-Nearest Neighbor (kNN) for the subject-independent scenario. For the subject-dependent scenario, the accuracy can reach over 95%. It proves that the proposed method can recognize different sleep postures effectively.

A Gm-compensated 46-101 GHz broadband power amplifier (PA) for high-resolution FMCW radars is presented in this paper. For bandwidth (BW) expanding, a Gm compensator-based negative feedback chain is applied to the PA, compensating the large gain ripple caused by a high-k transformer (TF)-based ultra-wideband interstage matching network (IMN). Based on the proposed Gm-compensated technique, a flat and ultra-wideband power gain of the PA can be obtained with the high-k TF-based IMN. The proposed PA achieves a 55-GHz BW without additional area overhead and efficiency loss. 74.8% of the fractional BW is obtained with

Machine learning inference engine is of great interest to smart edge computing. Compute-in-memory (CIM) architecture has shown significant improvements in throughput and energy efficiency for hardware acceleration. Emerging nonvolatile memory (eNVM) technologies offer great potentials for instant on and off by dynamic power gating. Inference engine is typically pre-trained by the cloud and then being deployed to the field. There is a new security concern on cloning of the weights stored on eNVM-based CIM chip. In this paper, we propose a countermeasure to the weight cloning attack by exploiting the process variations of the periphery circuitry. In particular, we use weight fine-tuning to compensate the analog-to-digital converter (ADC) offset for a specific chip instance while inducing significant accuracy drop for cloned chip instances. We evaluate our proposed scheme on a CIFAR-10 classification task using a VGG- 8 network. Our results show that with precisely chosen transistor size on the employed SAR-ADC, we could maintain 88%~90% accuracy for the fine-tuned chip while the same set of weights cloned on other chips will only have 20~40% accuracy on average. The weight fine-tune could be completed within one epoch of 250 iterations. On average only 0.02%, 0.025%, 0.142% of cells are updated for 2-bit, 4-bit, 8-bit weight precisions in each iteration.

Integration with the curvilinear, soft, and time-dynamic surfaces of the human body is critical for most implantable and wearable biomedical systems. Devices that can imitate the mechanics of the body provide opportunities to create human-machine interfaces. Additionally, wireless functionality is essential to monitor health/wellness, study disease conditions, and execute other functions. The use of metamaterials in wireless applications is becoming widespread due to its extraordinary properties such as evanescent wave amplification and negative refractive index. This paper studies a soft, flexible and stretchable Complementary Split Ring Resonator (CSRR) metamaterial energy harvester using a volume of 5.6 × 5.6 × 1 mm 3 on a Polydimethylsiloxane (PDMS) substrate. The CSRR is backed by a ground plane to absorb the incident power, and a via (load) is used to maximize the power harvesting efficiency. For stretchability, a typically rigid patch of the CSRR is replaced by the serpentine mesh. From the ANSYS HFSS simulation, it is found that the serpentine structure helps to reduce the size of the CSRR due to an increase in electrical length. The structure can also achieve high-quality factor (Q-factor), thereby enabling almost unity efficiency. The CSRR metamaterials can be used in future for wireless applications to integrate with the skin, the heart, and the brain.

The paper presents a sub-nW BJT based temperature sensor for ultra-low power microsystems. The sensor is based on amplifying the difference between base­emitter voltages of BJTs using gate-leakage transistors. Implemented in UMC 65nm technology, the sensor occupies an area of 0.005mm2. It achieves a maximum non-linearity error of 0.12oC(3σ) over the temperature range of — 55oC to 80o C. Without any trimming, a worst case inaccuracy of +0.36oC/ — 1.61oC is observed w.r.t process variations, depicting the process-invariant nature of the temperature sensor. It also achieves a low supply sensitivity of 0.56oC/V over a wide supply range of 0.7V-3V. The power consumption of the sensor is 419pW at 27o C and 0.7V supply.

A CMOS-only and multiple-output voltage reference has been proposed and simulated in a standard 0.18 μm CMOS process in this paper. Three reference voltages with their own advantages simultaneously are obtained based on the body bias technology and specific active load. Among the three references, the best temperature coefficient (TC) of 74.8ppm/°C in the range from -20°C to 80°C is obtained without using resistors and specific devices. By introducing amplifier and pushing away the main pole of the circuit, low line sensitivity (LS) of 0.06%/V and high power supply rejection ratio (PSRR) of -73dB at 10Hz are obtained without capacitor. Besides, due to the subthreshold operation, the current is as low as 77nA with a supply voltage down-to 1V.

The popularity of convolutional neural networks and deep learning based approaches has increased continuously in the past years. These methods has enabled the solution of various practical problems, but they still are not heavily exploited in the embedded domain, which requires low-power implementation of these architectures. Cellular neural networks can provide an analogue and power-efficient implementation of these networks which also enables the exploitation of non-Boolean, beyond CMOS elements such as memristive structures. In this paper we will demonstrate on simple datasets how cellular neural networks with different cell dynamics can be efficiently applied in the problem of semantic segmentation.

This paper presents an anti-overcharged high-dV/dt-immunity capacitive level shifter with dynamic discharge control (DDC) for half-bridge GaN driver. The DDC prevents overcharge of the floating power supply capacitor during high negative dV/dt transitions and is suitable for a wide variation range of negative dV/dt transitions of floating power supply. Moreover, a fault-logic blanking block is introduced to guarantee the robust of output logic during ultra-high dV/dt transitions. The proposed Level shifter is fabricated in a 0.18µm BCD process and occupies an active chip area of 0.034mm2. Simulation results demonstrate that the propagation delay is less than 0.8ns at 50V level shifting and keeps almost constant when the floating ground ranges from -3V to 50V. The positive dV/dt immunity is 300V/ns. The negative dV/dt is 170V/ns under the condition that the level shifting capacitor does not discharge to floating power supply.

This paper presents a comprehensive analysis of hardware accelerators for neural networks in both the digital and time domains, where the latter includes spatially unrolled (SU) and recursive (REC) architectures. All accelerators are implemented and synthesized in a 65nm CMOS technology. An identical neural network model is implemented in the digital and time domain for comparative purposes in terms of throughput, power consumption, area, and energy efficiency. Post-synthesis results show that SU achieves the highest energy efficiency of 145 TOp/s/W with a throughput of 4 GOp/s. The digital core is the fastest among other cores, whereas REC is the slowest but is the most area-efficient, occupying 0.114 mm2. SU is more suited for applications with stringent power constraints and average performance, while REC is better suited for applications where the area is the most important requirement and the throughput is less significant. In contrast, the digital core is preferable for large neural networks and critical applications that require high performance.

The paper proposes a method for guard-band customization to improve the energy efficiency of commercial FPGA. We deploy custom delay-based sensors alongside any user design to indirectly monitor, in real-time, the functional integrity of the target under voltage scaling. We develop a reliable sensing mechanism and regulate the FPGA operation by holistically considering process, voltage, and temperature variations during run-time. Tests with Xilinx Zynq SoC FPGAs and real benchmarks show significant power savings, in the area of 16-27%, while preserving nominal timing performance for only 1.6% resource overhead.

This paper presents a delay measurement technique leveraging the high accuracy in the amplitude/frequency measurements of a spectrum analyzer. The two signals whose phase difference is to be measured are combined to generate a single output that can be fed to the spectrum analyzer. The delay information is embedded in the form of phase modulation in this output signal, resulting in a spur at one-fourth of the input signal frequency. The magnitude of this spur is used for estimating the input delay. Monte Carlo simulations of the proposed method for an input delay of 10 ps gives an estimated delay with a mean of 10.25 ps and a standard deviation of 1.17 ps.