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In this work, physical insights into missing SCR action in High Voltage drain extended FinFET SCR is developed using detailed 3D TCAD simulations. The 3D TCAD simulations revealed that the missing SCR action in STI-DeFinFET SCR is due to the weak bipolar strength associated with the PNP corresponding to the anode (P+) contact. A novel Dual-Fin STI DeFinFET SCR architecture is revealed to address this roadblock and achieve SCR action in these devices, which offered a failure threshold 3X times higher than the conventional device. Furthermore, to investigate the filament behavior, a 64-Fin Dual-Fin STI DeFinFET SCR is simulated, revealing severe filament driven low current failure in these devices. Silicide blocking and well-implant engineering were found to improve power scalability issues in these devices.

The behavior of gate grounded vertically stacked nanosheet N-FET (ggNFET) under ESD stress is investigated in this work. Single Fin (3-Sheet) ggNFET devices exhibit multiple instability points in the TLP-IV characteristic around the snapback region. Each of these instabilities was found to be arising due to non-uniform sheet turn-on and was independent of the presence of body contact. However, this instability was more severe, with a decreased body distance from the source. Furthermore, the sequence of turn-on was found to be dependent on the TLP current ramp rate. A 24-Fin (72 Sheet) ggNFET was simulated to reproduce the current filament like behavior. These 24- Fin simulations revealed a more severe low-current instability due to both non-uniform sheet turn-on and non-uniform Fin turn-on. For a smaller body to source contact distance, this non-uniform turn-on was seen to result in an early failure of the device.