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In this work, the modeling of spiking neurons and their VLSI implement issues are evaluated and discussed in detail in terms of silicon area, power, and stability considering nanometer technologies process, voltage, and temperature variations. Considering low power requirement and stability, Hindmarsh-Rose model turns out to be the best choice for neural network implementation because of its affordable cost and rich neural features. Although other models such as Leaky Integrate-and-Fire model costs less, it is limited by its poor neural plausibility.

Multi-threshold null convention logic (MTNCL) is a commonly used asynchronous paradigm for designing low power NCL circuits. Traditionally, MTNCL circuits implemented using complementary metal oxide semiconductor (CMOS) technique that tends to occupy a large area. To address this limitation, a gate diffusion input (GDI) methodology is introduced for implementing MTNCL circuits. This GDI technique enables complex logic to be implemented using only two transistors that helps to reduce area utilization. In this paper, a novel approach to implement MTNCL designs based GDI methodology is proposed. The proposed approach has been verified by implementing TH23 MTNCL gate. Comparing to the conventional CMOS implementation, the proposed approach shows a 45% reduction in the area overhead.

Null convention logic is a commonly used delay insensitive paradigm for designing asynchronous circuits. Traditionally, NCL circuits are implemented using static complementary metal oxide semiconductor (CMOS) technology that tends to have large area overhead. To address this issue, a gate diffusion input (GDI) methodology is introduced for realizing NCL circuits. This GDI is a low-power design approach that uses only two transistors to design complex circuits. By using this design technique, a significant reduction area utilization was observed at the expense of latency overhead. To address this limitation, a novel design approach based on GDI methodology is proposed in this paper. The proposed fast GDI (FGDI) approach uses GDI functions F1 and F2 to reduce latency without affecting performance. To evaluate the performance of the FGDI technique, a one-bit full adder was realized in Cadence virtuoso 45nm technology. Compared to GDI implementation, FGDI approach shows a 76% reduction in the latency.

Graphical Processing Units (GPUs) are always criticized for high power consumption due to its massive performance that it can deliver. While GPUs are getting into the mobile market, more power constraints are established. In this work, we evaluate the power gating techniques for GPU cache arrays. The leakage power in active mode is measured at 2.28 µW whereas is sleep mode leakage power is measured at 0.61 µW (26.7% of active mode leakage) and 0.034 µW at off mode (1.5% of active mode leakage) at 1.0V power supply using 45nm standard CMOS process.

Cardiovascular diseases (CVDs) are the number one cause of death today. Therefore, the early detection of arrhythmia is very important for cardiac patients. This paper proposes the heartbeat classification algorithm using the electrocardiogram(ECG) signals. An ECG is a 1D signal that is the result of recording the electrical activity of the heart using an electrode. In this paper, a single-layer Tensorflow LSTM model has been proposed to classify a biological time-series consisting of normal and abnormal heartbeats. The method was evaluated using the publicly available Physio net's MIT-BIH Arrhythmia dataset. The dataset has been divided into training and testing data. As a result, the classifier achieved a 95% average accuracy. Compared with the other CNN and RNN models used for the heartbeat classification, the simulation result shows the proposed algorithm has higher accuracy.

The paper presents standing wave oscillator-based clock distribution minimizing equivalent capacitance (c d ) for process and temperature variation. The SWOs have been proposed to enhance the negative resistance g d (an equivalent transconductance per ccp) to cancel the conductance in a transmission line. However, the SWOs have a parasitic capacitance which affects clock phase and unit length of the transmission line. In the proposed SWO, a MOS varactor, C var (V) (voltage-controlled capacitance), is added to minimize c d (equivalent capacitance per ccp). A phase locked loop and other peripherals are added to adjust the frequency and c d because the target frequency in the SWO varies due to process and temperature variation The design is simulated by a 180nm CMOS technology node with 1.8V power supply, and the total power consumption is 31.841 mW for the proposed architecture.