1. A 65 fps Full-HD Hardware Implementation of HOG, HOF, MBHx, and MBHy for Real-Time Action Recognition
- Author
-
Jia-Lin Chen, Liang-Gee Chen, and Zhi-Yi Lin
- Subjects
Hardware architecture ,Computer science ,business.industry ,Computation ,Feature extraction ,02 engineering and technology ,01 natural sciences ,010309 optics ,Gate count ,Histogram ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,System on a chip ,business ,Throughput (business) ,Computer hardware - Abstract
In this paper, we propose a compact hardware architecture which can support HOG, HOF, MBHx and MBHy feature extraction in real-time. To achieve low-cost hardware, we first design a hardware-oriented algorithm. In addition to simplification of complicated numeric computation, we also modify the computation of the gradient at boundary to reduce on-chip buffers. The architecture is highly parallel in order to fully reuse input data and to achieve high throughput. Other features of our architecture include a four-bank memory composed of four SRAMs, a 2-cycle weighted binning, and a 2-port memory for histogram collection. The final specification can support HOG, HOF, MBHx, and MBHy feature extraction with a throughput of 65 fps in full-HD videos operating at 215 MHz, consuming only 57.6 kB on-chip memory and a gate count of 411k.
- Published
- 2018