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In the present work, the impact of high-k spacers and Negative Capacitance (NC) has been examined on the performance of nanoscale Double Gate Junctionless Transistors by self consistently solving Landau Khalatnikov equation with TCAD simulations. Ferroelectric hafnium oxide is considered in gate stack with interfacial layer of silicon dioxide. The impact of different dielectric constants of spacer and different spacer lengths have been explored extensively on various electrical parameters. It has been demonstrated that high-k spacers significantly improve the gate controllability, thereby, further enhancing the negative capacitance (NC) effect of ferroelectric layer on device operation. The subthreshold swing values as low as 10mV/dec have been obtained along with substantial improvement in I on /I off ratio (about 3 orders), thereby, indicating suitability of the device for future ultra low power electronic applications.

In the present work, performance of short channel symmetric Double Gate Gaussian Doped Ferroelectric FET (DGGDFEFET) has been studied by using fully coupled TCAD simulations with Landau Khalatnikov equation. Ferroelectric layer of PVDF-TrFE (polyvinyledenedifluoride-trifluoroethylene) is considered as gate insulator with an intermediate layer of SiO 2 . The channel is non-uniformily doped in vertical direction and the analog and digital performance of DGGDFEFET has been investigated by obtaining transfer characteristics, subthreshold swing, transconductance ($g_{m}$), transconductance generation factor (TGF), output characteristics and output conductance ($g_{d}$). It has been demonstrated that due to negative capacitance and vertical non-uniform doping, DGGDFEFET shows superior analog and digital performance since it offers super steep transfer characteristics and substantially improved TGF and output characteristics.