1. Low-power null convention logic design based on modified gate diffusion input technique
- Author
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Yong-Bin Kim, Prashanthi Metku, Minsu Choi, Ramu Seva, and Kyung Ki Kim
- Subjects
010302 applied physics ,Adder ,Computer science ,Semiconductor device modeling ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,Integrated circuit design ,021001 nanoscience & nanotechnology ,01 natural sciences ,Logic synthesis ,CMOS ,Logic gate ,0103 physical sciences ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,0210 nano-technology ,Hardware_LOGICDESIGN ,Asynchronous circuit ,Electronic circuit - Abstract
Null Convention Logic (NCL) is the one of the well-known clock-less approaches for designing asynchronous logic circuits. The complementary metal oxide semiconductor (CMOS) technology is usually used for implementing the NCL circuits, which as a major drawback of large area consumption and power dissipation. These limitations have been addressed by adopting a low-power design technique called Gate Diffusion Input (GDI) in this work. GDI technique allows implementing primitive logic gates using only two transistors. Thus, it not only reduces the transistor count but also the power consumption. However, GDI technique suffers a significant voltage drop across the circuit, due to its inherent voltage swings. Thus, to ensure full swing output regenerative buffers are added at the output stage which tends to increase the overall latency. In this work, a novel GDI and HYBRID (CMOS+GDI) designs are proposed to overcome the limitations of the CMOS-NCL designs. The proposed approaches were tested by realizing NCL Ripple Carry Adder (RCA). The proposed model was simulated in Cadence Virtuoso and power reduction of 14.9 % and 9.8 % has been observedfor GDI and HYBRID models, respectively.
- Published
- 2017
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