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Null Convection Logic is a well-known paradigm for designing asynchronous logic circuits. The conventional CMOS-based NCL designs suffers larger area overhead and power consumption. A low power design technique called Gate Diffusion Input (GDI) has been adopted to overcome this limitation. In GDI technology, voltage swing exhibits significant voltage drop across the circuit. Therefore, not suitable for designing large combinational circuits. A novel HYBRID (CMOS+GDI) design is proposed in this work to efficiently address this issue. The HYBRID design utilizes both CMOS and GDI technology to reduce the number of transistor and power dissipation when compared to CMOS NCL circuits. The proposed approach is implemented in NCL Ripple Carry Adder (RCA) and simulated in Cadence Virtuoso for verification.

3D heterogeneous processor (commonly termed as 3DHP) integrating multiple processor (such as CPU/GPU) and DRAM dies vertically interconnected by a massive number of Through-Silicon Vias (TSVs) is expected to address the limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability due to hotspots in on-chip thermal gradient may result in wide bit error rate variation in DRAM dies. A multi-path BCH decoder has been recently proposed to efficiently address this issue. In this paper, a novel parallel decoding approach for the Multi-Stage BCH decoder is proposed and validated. The proposed approach efficiently leverages the multiple decoding paths to decode multiple words and minimizes the overall decoding latency.

This paper proposes presents a low power and high-speed four-quadrant analog multiplier in the current mode based on dual translinear loops using 32nm CMOS and 32nm CNTFET technologies to investigate and compare the performance differences of the analog circuits on CNTFET technology and CMOS 32nm technology nodes. All the simulations were performed using hspice with 32nm CMOS from PTM library and 32nm CNTFET from Stanford University technologies at the same power supply level. CNTFET based multiplier shows a wider linearity over considerable range of outputs (−10 μA to +10μA) while the CMOS based multiplier shows (−7μA to +7μA) and the 3db frequency of the CNTFET based multiplier is 110GHz while the 3dB frequency of the CMOS based multiplier is only 2.45GHz.

This paper presents a UHF RFID Reader designed for recognition and tracking in IoT domain. It is built by NI USRP software radio platform and NI LabVIEW with flexible physical/MAC layer parameters, which can be modified easily and monitored clearly from front panel of this Reader compared to commercial RFID Reader. Queried random number sequence from a commercial Tag can be detected within half meter using this UHF Reader. All designs of this Reader are based on EPC Gen-2 RFID protocol, any further research based on this Reader can be easily connected and tested with commercial Tags.

SC (stochastic computation) has been found to be very advantageous in image processing applications because of its lower area consumption and low-power operation. However, one of the major issues with the SC is its long run-time requirement for accurate results. In this paper, a new technique called the approximate stochastic computing (ASC) approach called the approximate stochastic computing (ASC) focusing on image processing applications is proposed to reduce the computation time of a SC by a factor of 16 at a trade-off of an error percentage of 3.13% in the absolute stochastic value ([0,1)) computed. The proposed technique considers only the first four MSBs of the image pixel value for SC, which introduce a maximum error of 6.25% in the stochastic output. Attempts have been made to reduce this error to 3.13% by linearly increasing the clock cycles from 16 to 17 rather than exponentially (ex: 32, 64,128,256…). Experimental results from SC edge detection circuit indicate that this technique is a promising approach for efficient approximate image processing.