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In the recent times, various challenges are being encountered during SRAM cache design and development which lead to a situation of converting the memory cell technologies into on-chip embedded caches. The current research statistics towards cache designing reveals that Spin Torque Transfer Magnetic RAMs, preferably termed as STT-MRAMs has become one of the most promising areas in the field of memory chip design. Hence, it gained a lot of attention from the researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. time and energy optimization. Instead of having efficient main memory access capability, STT-MRAMs suffer due to high error rate caused during stochastic switching in write operations. Cache replacement algorithms play a significant role in minimizing the error rate in write operations. The proposed study aims to offer a theoretical and analytical modeling of an efficient cache replacement scheme to overcome the error as mentioned above in L2-STT-MRAM caches. The performance analysis of the proposed algorithm ensures its effectiveness in reducing the error rate and cost overheads as compared to the conventional LRU technique implemented on SRAM cells.

Cache Replacement Policies play a significant and contributory role in the context of determining the effectiveness of cache memory cells. It has also become one of the major key features for efficient memory management from the technological aspect. Hence, owing to the existing critical computing systems, it has become too essential to attain faster processing of executable instructions under any adverse situations. In the current scenario, the state of art processors such as Intel multi-core processors for application specific integrated circuits, usually employ various cache replacement policies such as Least Recently Used (LRU) and Pseudo LRU (pLRU), Round Robin, etc. However, fewer amounts of existing research works are found till date to utter about explicit performance issues associated with the conventional cache replacement algorithms. Therefore, the proposed study intended to carry out a performance evaluation to explore the design space of conventional cache replacement policies under SPEC CPU2000 benchmark suite. It initiates and configures the experimental Simple Scalar toolbox prototype on a wide range of cache sizes. The experimental outcomes obtained from the benchmark suite show that PLRU outperforms the conventional LRU concerning computational complexity and a variety of cache blocks organization.