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GPU (Graphics Processing Unit) is emerging as a key 3D/2D graphics and parallel workload accelerator in various SoC applications. As semiconductor fabrication technology continues to scale, chips (especially those with extremely high transistor counts such as processors) are becoming increasingly vulnerable to faults that could produce unwanted errors in computing. The most severe problem is Silent Data Corruption (SDC) because this fault insidiously generates erroneous outputs without being detected. This paper discusses the characterization of SDC vulnerability of GPU on various GPGPU (General Purpose computing on GPU) workloads.

3D heterogeneous integration (commonly termed as 3DIC) of CPU, GPU and DRAM dies vertically interconnected by a massive number of TSVs (Through-Silicon Vias) is expected to overcome limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability in temperature (i.e., hotspots) is anticipated to result in bit error variation in DRAM die. A novel multi-stage BCH decoder has been proposed to efficiently address this issue in this work. The proposed multi-stage BCH decoder is designed to tolerate upto a certain maximum number of error bits per codeword, which is estimated from the on-line thermal gradient data, to minimize the decoding latency.

Hand detection plays an important role in Human Computer Interaction (HCI). Most of the existing hand detection methods rely on the contour shape of hand after skin color segmentation. Such contour shape based approaches, however, are easily distorted by noises and other skin color segments. In this paper, we present a distance image based approach using CPU-GPU heterogeneous computing. Our experiments demonstrate that our proposed distance image based hand detection is robust and fast, reaching up to 97.32% palm detection rate where 80.36% of cases have more than 3 fingers detected on commodity processors. We also achieved 5.0 times speed-up for 320×240 images, and 17.5 times for 640×480 images.

Internet of Everything (IoE), embedded with microcontrollers and wireless technologies onto a single system on a chip (SoC), are able to be connected with other devices in the cloud. Wearable sensors and RFID are core technologies in IoE. Energy efficiency and miniaturization are the two most critical technical challenges for the hardware implementation of microelectronic systems enabling Internet of Everything. Low-power smart systems on a chip are the key enabling solutions. In this paper, we outline the key hardware components and design challenges of BSN.

This paper presents low power and low jitter phase locked loop (PLL) design using supply regulation and active loop filter (ALF) on 110nm CMOS technology and with 1V supply voltage. The supply voltage is regulated by low-dropout (LDO) regulator. The ALF filters high frequency noise of the VCO control voltage. The LDO regulator provides 0.8V output, −83 dB PSRR with PLL load, 0.578mW power consumption, and 99.8% current efficiency with 40mA load current. The jitter of the PLL without and with LDO regulator is 44.9ps and 4.6ps, respectively.