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This work presents a study of the CMOS based R-2R ladder network (also called M-2M) Digital-to-Analog Converter (DAC) as a potential candidate for ultra-low voltage (ULV) applications, i.e. supply voltages VDD lower than 200mV. MOS transistors operate in subthreshold under such very low VDD, and the circuit analysis must be done using an all-region continuous MOSFET model. Simulation results in a commercial 130 nm process corroborate the presented analysis, showing that it is possible to implement this DAC topology for 6 to 8 bits operating under supply voltages from 70 mV to 140 mV.

This paper describes the design and implementation of a low-pass third-order single-loop single-bit continuous-time sigma-delta modulator (CT-SDM) in a 130 nm CMOS process. To reduce clock jitter effects and operational amplifiers requirements a non-return-to-zero (NRZ) digital-to-analog converter (DAC) pulse shape was employed. Post-layout simulation results indicate that the modulator achieves 56 dB of dynamic range, 57.31 dB of peak SNDR or 9.23 bits of effective resolution over a 1 MHz signal bandwidth with an oversampling ratio (OSR) of 64. The CT-SDM draws 5.91 mW from a 1.2 V power supply providing a figure-of-merit (FOM) of 4.93 pJ/conv. The CT-SDM core area is 0.31 mm2 and the chip was manufactured and will be soon characterized.

The MOSFET Zero Temperature Coefficient (ZTC) condition is a strategy that can be used to implement low temperature sensitivity circuits, such as current and voltage references. This condition is usually analyzed using the strong inversion quadratic MOSFET model. In this work we use a different approach, based on a continuous MOSFET model that can predict its behavior from weak to strong inversion. Based on this analysis, we verify that the ZTC point occurs from moderate to strong inversion for any CMOS process, since this point must occur for gate-source voltages larger than one threshold voltage. Also, a resistorless switched capacitor current reference based on the ZTC condition (ZSCCR), presenting low temperature coefficient (TC), is presented. The ZSCCR is designed in a 180 nm process, resulting a reference current of 5.88 µA under a supply voltage of 1.8 V, and occuping a silicon area around 0.010mm2. Results from circuit simulation show an effective temperature coefficient (TC eff ) of 60 ppm/°C from −45 to +85 °C and a power consumption of 63 µW.