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Start Over Author "Punyashloka Debashis" Journal 2014 international conference on simulation of semiconductor processes and devices (sispad)
1 results on '"Punyashloka Debashis"'

1. A FinFET LER VT variability estimation scheme with 300× efficiency improvement

Author

Udayan Ganguly, Punyashloka Debashis, Sushant Mittal, and Sabareesh Nikhil Chinta

Subjects
Electronic engineering, Node (circuits), Topology, Line edge roughness, Sensitivity (electronics), Communication channel, Threshold voltage, Mathematics, Fin (extended surface)
Abstract

In this paper, we have proposed a computationally efficient method to evaluate threshold voltage (V T ) variability due to Line Edge Roughness (LER) in sub-20nm node FinFETs. For channel lengths less than 15 nm, the variability in threshold voltage may be estimated to a great accuracy (error T from LER specifications of a fin patterning technology.

Published
2014

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