1. FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node
- Author
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R.O. Jung, Muthumanickam Sankarapandian, Kangguo Cheng, R. Johnson, Miaomiao Wang, Balasubramanian S. Pranatharthi Haran, E. Augendre, Pierre Morin, Bruce B. Doris, Y. Escarabajal, B. Lherron, S. Pilorget, J. L. Bataillon, M. Vinet, Walter Kleemeier, Sean Teehan, J. Kuss, Emmanuel Josse, T. Levin, F. Chafik, Joel Kanyandekwe, Michel Haond, S. Guillaumet, Olivier Weber, D. Chanemougame, R. Sampson, B. Liu, Nicolas Loubet, B. DeSalvo, Tenko Yamashita, L. Grenouillet, Sylvain Maitrejean, Frederic Allibert, Qing Liu, O. Faynot, M. Celik, Rajasekhar Venigalla, Thomas Skotnicki, H. Kothari, Mukesh Khare, Frederic Boeuf, and H. He
- Subjects
Materials science ,CMOS ,business.industry ,Electrical engineering ,Gate length ,Optoelectronics ,Node (circuits) ,Substrate (electronics) ,business ,Communication channel - Abstract
We report FDSOI devices with a 20nm gate length (L G ) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V dd of 0.75V, competitive effective current (I eff ) reaches 550/340 µA/µm for NFET, at I off of 100/1 nA/µm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V dd of 0.75V, PFET I eff reaches 495/260 µA/µm, at I off of 100/1 nA/µm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.
- Published
- 2014