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In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Three dimensional integration circuits technology has received much attention recently since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are essential. In the current types of interconnects, solder micro bumps have been widely used and thermocompression bonding process are well adopted to form the connection between bumps. However, the prefect joint contour is difficult to obtain and control by such kind of bonding process in solder micro bump joints. For fine-pitch solder micro bump interconnections, the effect of joint shape on the reliability performances of the solder micro bump joints is not concluded yet till now and needs to be clarified. In this study, the effect of joint shape controlled by thermocompression bonding on the reliability performance of solder micro bump interconnections with a pitch of 60 um was discussed. The chip-to-chip test vehicle having more than 4000 solder micro bump interconnections with a bump pitch of 60 um was used in this study. A solder micro bump structure of Cu/SnAg having a thickness of 7 um/10 um was fabricated in both the silicon chip and substrate. To evaluate the effect of joint shape, four types of joint shape were controlled and made. The first type had a conventional shape of micro joint. Compared to the first one joint structure, the second type of joint structure showed the compressed shape. The third type of joint structure was the pillar-like micro joint while the fourth type of joint structure presented a neck shape having the highest joint height among all the joint structures tested. We used the fluxless thermocompression bonding process to form these four types of micro joints. After bonding process, the chip stack was assembled by capillary-type underfill. Reliability tests of temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were selected to assess the effect of joint shape on the reliability properties of those four types of solder micro bump interconnections. The reliability results presented that all the types of joint structures could pass TCT of 1000 cycles and HTS of 1000 hours but high variation of daisy chain resistance more than 15% would happen in the neck-shape micro joint after TCT. For the neck-shape micro joint, the high variation of daisy chain resistance after TCT resulted from the cracking propagated along the interface of Cu UBM/Cu 6 Sn 5 IMC and across the tin solder. The cracking situation was more serious as compared to the other three tested micro joints. The results of HTS revealed that resistance variation mainly depended on the micro structural evolution within micro joints tested. Electromigration test was conducted under the testing condition of 0.56 A/150°C. A daisy chain structure was adopted. For both the pillar-shape and neck-shape micro joints, Cu UBM consumption and formation of large void were the major microstructure evolutions within the micro interconnections during EM testing. The conpressed-shape showed the longer electromigration lifetime among all the types of micro joints tested.

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.