1. A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies
- Author
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Seong-Je Kim, Dongkyu Lee, Jung-Gil Yang, Zhenhua Wu, Ho-Kyu Kang, Keun-Ho Lee, Eun-Sung Jung, Wouns Yang, Won-Sok Lee, Jung-Dal Choi, Young-Kwan Park, Taehyun An, Sang-Su Kim, Sung-Gi Hur, Kab-Jin Nam, and Uihui Kwon
- Subjects
Materials science ,Fabrication ,business.industry ,Transistor ,Nanowire ,Silicon on insulator ,Equivalent oxide thickness ,Nanotechnology ,law.invention ,Parasitic capacitance ,law ,Logic gate ,MOSFET ,Optoelectronics ,business - Abstract
This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC and AC performances of Si NW MOSFETs on NW diameter (DNW) and gate oxide thickness has been investigated. A Si NW device with the scaled DNW of 9 nm and thin equivalent oxide thickness (EOT) of 0.9 nm improved both on-current and electrostatic characteristics. Finally, a Nanowire-On-Insulator (NOI) structure has been proposed to enhance the AC performance of a multiple-stacked NWs structure, which improves DC performance but has the issue of high parasitic capacitance. As a result, the simulated AC performance of a triple-NOI structure was improved by around 20% compared to conventional triple NW structure.
- Published
- 2013