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It is critical that more architectural registers are available to the compiler and programmer, as a small number of architectural registers might hinder the compiler and programmer from producing efficient code. Although modern chip manufacturing processes could easily put many registers on an ARM processor, only 16 general registers are accessible by the compiler and programmer. Doubling the number of architectural registers requires adding another bit to each register field of instructions, and hence increases code size. One approach has been developed to use the underutilized condition bits to double the number of architectural registers from 16 to 32 but maintain the width of ARM instructions. Although performance gain can generally be achieved by most of benchmark programs on a 32-register ARM, this approach would still hurt performance for programs with high ratios of instructions that can be conditionalized. Therefore, a better approach would to keep the conditional execution feature even when the 4-bit condition field is used to encode the extra registers. This paper proposes to borrow the IT instruction from Thumb II ISA to represent the predicates of conditionalized instructions on the 32-register ARM. GCC and SimpleScalar/ARM have been modified to handle the new instruction format and the revised IT instruction, and experimental results have shown that performance can be improved by 10.4% on average for MediaBench II benchmarks on the 32-register ARM with conditional execution. [ABSTRACT FROM PUBLISHER]

Presents an index of the authors whose articles are published in the conference. [ABSTRACT FROM PUBLISHER]