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Supply voltage (V DD ) scaling has been an important issue as the CMOS scaling down. Scaling of devices induces large leakage current due to Short Channel Effects (SCEs). Also, Subthrehold Swing (SS) value of CMOS devices is theoretically limited to 60 mV/dec. Various structures have been proposed to overcome power dissipation problems, one of which is the TFETs [1–2]. However, TFET has two critical drawbacks such as low on-current level and ambipolar behaviors. To overcome these disadvantages, TFET using hetero-gate dielectric materials has been lately reported [3]. Although this TFET has low SS and high on-current level, it is difficult to control dielectric alignment between high-k material and SiO 2 in the process. Thus, we introduce an improved TFET in terms of fabrication and performance.

Modern VLSI technology has been developed with continuous scaling of MOSFET. However, as MOSFET has been scaled down, a lot of critical issues have risen and resulted in a considerable degradation of individual devices [1]. On the other hand, owing to its periodic on/off characteristic, single-electron transistor (SET) attracts attention with its promising performance. But, in general, fabricating SET, silicon-on-insulator (SOI) wafers have been used for their leakage current through buried oxide (BOX) on the substrate region [2]. However, in this paper, we propose a vertical structure that is fabricated on a bare wafer, not on a SOI wafer, and the fabrication process with which small size of a quantum dot (QD) can be formed more easily than previous works [1][3]. Since the smaller QD a SET has, the better operation characteristic it has at room temperature (RT), the characteristic of the SET device can be observed more clearly than previous works with the simple process to downsize a QD.