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The paper describes the design of a front-end chip for hybrid pixel detectors optimized for good timing resolution (200 ps rms) and high event rate (150 kHz per pixel). Each channel consists of a fast transimpedance amplifier with 5 ns peaking time, a constant fraction discriminator (CFD), and a Time-to-Digital Converter (TDC). In order to cope with the rate requirement, a multi-event buffering scheme employing both analog and digital pipelines is implemented in each cell. This development is part of the R&D activity for the silicon tracker of the NA62 experiment at CERN. The architecture of the chip and the design of the critical building blocks are discussed in the paper.

The renewal of interest in Time of Flight Positron Emission Tomography (TOF-PET), as well as the necessity to precisely tag events in high energy physics (HEP) experiments at future colliders are pushing for an optimization of all factors affecting the time resolution of the whole acquisition chain comprising the crystal, the photo detector, and the electronics. The time resolution of a scintillator-based detection system is determined by the rate of photo electrons at the detection threshold, which depends on the time distribution of photons being converted in the photo detector. The possibility to achieve time resolution of about 100 ps Full Width at Half Maximum (FWHM) requires an optimization of the light production in the scintillator, the light transport and its transfer from the scintillator to the photo detector. In order to maximize the light yield, and in particular the density of photons in the first nanosecond, while minimizing the rise time and decay time, particular attention must be paid to the energy transfer mechanisms to the activator as well as to the energy transition type at the activator ion. Alternatively other light emission mechanisms can be considered. We show that particularly Cerenkov emission can be used for this purpose. Special emphasis was put on the light transport within the crystal and at its interface with the photo detector. Since light is produced isotropically in the scintillator the detector geometry must be optimized to decrease the optical path-length to the photo detector. Moreover light bouncing within the scintillator, affecting about 70\% of the photons generated in currently used crystals, must be reduced as much as possible. We also investigate photonics crystals that are specifically designed to favor specific light propagation modes at the limit of total reflection inside and outside of the crystal and how they might increase the light transfer efficiency to the photo detector and hence improve time resolution. Examples for the production and deposition of photonics crystals as layers on Lutetium Yttrium Ortho-Silicate (LYSO) and Lutetium Yttrium Aluminum Perovskite (LuYAP) crystals are shown here, as well as first results on an improved light extraction resulting from this method.

We present the design and test results of a front-end prototype circuit developed in 130 nm CMOS technology for the readout of the Gigatracker pixel detector experiment in NA62 at CERN. The main challenges for the front end amplifier are very high signal hit rate (dead time less than 100ns, average signal rate 100 kHz) and 100 ps timing resolution combined with the level of affordable power consumption (< 2W/cm2) and noise (< 200 e−ENC). The predicted ENC levels for the nominal detector capacitance of 250 fF and maximum leakage current of the order of 20 nA are below 200 e−. The overall power consumed by the analogue and digital part of the pixel cell is in the order of 130 μW. The optimization of the design as well as test results of the prototype front end chip are evaluated and discussed.