1. A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- Author
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S. S. Iyer, Hien Minh Le, Abraham Mathews, Gregory J. Fredeman, P. Wilcox, Hung Ngo, John E. Barth, Trong V. Luong, R. Freese, Peter Juergen Klim, Erik A. Nelson, G. Koch, John Golz, William Robert Reohr, Hillery C. Hunter, Jente B. Kuang, Paul C. Parries, A. Khargonekar, T. Kirihata, and D. Dick
- Subjects
Read-only memory ,Hardware_MEMORYSTRUCTURES ,Computer science ,business.industry ,Pipeline (computing) ,Hardware_PERFORMANCEANDRELIABILITY ,eDRAM ,CMOS ,Hardware_INTEGRATEDCIRCUITS ,Charge pump ,System on a chip ,Cache ,business ,Dram ,Computer hardware - Abstract
We present a 1 MB cache subsystem that integrates 2 GHz embedded DRAM macros, charge pump circuits, a 4 Kb one-time-programmable ROM, clock multipliers, and built-in self test circuitry, having a 36.5 GB/s peak system data-rate. The eDRAM employs a programmable pipeline, achieving a 1.8 ns latency.
- Published
- 2008
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