1. A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme
- Author
-
Sheng-Da Wu, Yi-Jui Tsai, and Hong-Yi Huang
- Subjects
Least significant bit ,CMOS ,Dynamic range ,law ,business.industry ,Computer science ,Electronic engineering ,Integrated circuit ,business ,Phase detector ,Computer hardware ,Electronic circuit ,law.invention - Abstract
This work presents a CMOS cycle time-to-digital converter (CDC) integrated circuit utilizing a two-level conversion scheme. The technique that allows the achievement of wide dynamic range is presented. The CDC is based on a multi-phase sampling and vernier delay line (VDL) used in conjunction with a synchronous read-out circuitry. The proposed CDC can provide high resolution with the high conversion rate. The CDC achieves 83.3 MEvents/sec conversion rate and 23-ps resolution, stabilized by the dual DLL. The DNL is less than plusmn 0.34 LSB (23 ps). The INL is plusmn 0.33 LSB.
- Published
- 2007