1. A 65nm 95W Dual-Core Multi-Threaded Xeon� Processor with L3 Cache
- Author
-
David J. Ayers, Simon M. Tam, Stefan Rusu, J. Chang, Sujal Vora, and B. Cherkauer
- Subjects
Smart Cache ,Snoopy cache ,Xeon ,business.industry ,Cache coloring ,CPU cache ,Computer science ,Pipeline burst cache ,Cache ,business ,MESIF protocol ,Computer hardware - Abstract
This paper describes a 95 W dual-core 64-bit Xeonreg MP processor implemented in a 65 nm 8 metal layer process. Each processor core has a unified 1MB L2 cache and supports the Intelreg Extended Memory 64 Technology and the Hyper-Threading Technology. The shared L3 cache has extensive RAS features including the Intelreg Cache Safe Technology and Error Correction Codes (ECC). The processor is designed and optimized to operate at a 95W thermal design power envelope at the target product frequency. The front-side bus operates at 667 MT/s or 800 MT/s in a 3 load topology that is compatible with existing platforms.
- Published
- 2006